VHDL Circuit Design, Simulation and FPGA Programming Using VIVADO

Calendar
When:
February 15, 2022 @ 11:00 am – 12:00 pm America/New York Timezone
2022-02-15T11:00:00-05:00
2022-02-15T12:00:00-05:00
Where:
Webinar
All Meetings HomePage

VHDL Circuit Design, Simulation and FPGA Programming Using VIVADO

Speaker:   Orhan Gazi, Cankaya University, Ankara-Turkey

Course Format: Live Webinar, 10 sessions, 1 hour per session

Times and Dates:  11AM (ET) February 15, 17, 22, 24, March 1, 3, 8, 10, 15, 17

Decision to run this course is:  Tuesday, February 8, 2022

 

 

IEEE Members:  $250.00

Non-Members:  $300.00

Introduction:  In this course VHDL circuit design language will be taught. VIVADO Platform will be used for VHDL coding, simulation and FPGA programming.  The attendee should have basic knowledge of digital circuit design. VHDL language is an  hardware design language. Its popularity is increasing in years. It is used to program FPGA devices. It is not exaggerating to say that most of the future electronic systems will include FPGA devices in their structures since FPGA devices are flexible, reconfigurable platforms for hardware designs.  The attendee taking this course will learn VHDL language and he or she will be able to make digital circuit design using VHDL language. Besides, the attendee will learn how to program FPGA devices for circuits designed using VHDL.

Prerequisite: The one who is interested in taking this course should have basic knowledge of digital logic design. He or She should be familiar with the terms binary encoders, decoders, multiplexers, counters, registers, etc.

  • Entity, Architecture and VHDL Operators
  • Project Creation Using VIVADO, Schematic, Synthesis
  • Internal Structure of FPGAs, LUTs, Slices
  • Combinational Logic Circuit Design and Concurrent Coding in VHDL
  • Testbench Writing and Simulation of VHDL Codes Using VIVADO
  • Constraint Files and FPGA Programming with VIVADO
  • User Defined Data Types in VHDL
  • Sequential Circuit Implementation in VHDL
  • Frequency Division in VHDL
  • Testing Sequential Logic Circuits on VIVADO
  • Packages, Components, Functions, and Procedures in VHDL
  • Fixed and Floating Point numbers in VHDL

Target Audience:  Electronic and Communication Engineers, electronic engineers, computer engineers, engineers working in communication industry

Benefits of Attending Course: 

1) The participant will learn how to design digital circuits using  VHDL.

2) The participant will learn how to create projects  and make simulations in VIVADO.

3) The participant will learn how to program an FPGA device.

4) The participant will have an idea about the architecture of FPGA device.

Speaker Bio:  Prof. Orhan Gazi is the author of the book “A Tutorial Introduction to VHDL Programming” https://www.springer.com/gp/book/9789811323089

Prof. Orhan Gazi is the author of 10 books written in electrical engineering subjects.

He is also one of the authors of the book “State Machines using VHDL: FPGA Implementation of Serial Communication and Display Protocols” which can be reached from https://www.springer.com/gp/book/9783030616977

The research area of Prof. Orhan Gazi involves “channel coding”, and “digital communication subjects”.  Recently, he focuses on over capacity data transmission using polar codes. He is also interested in practical applications of communication systems involving FPGA devices. He is delivering courses with titles “VHDL circuit design”, “interface design using VHDL for FPGA devices” and “system on chip design”.

Materials to be included:  Lecture slides will be provided.