Speaker: Steve Hoover, Redwood, EDA
Type of Course: Self-paced, on demand Course. Lab format
Dates: 9/1/2021 – 9/30/2021
Registration Deadline: Decision date to run/cancel this course: August 25, 2021
Register by Wednesday, August 25, 2021 for the early registration rate.
Members: $275.00 – Non-Members: $320
After August 25, 2021:
Members: $350.0 – Non Members: $395
Course Overview: CPUs are a fundamental building block of complex SoCs, and RISC-V is taking hold as the ISA of choice. In this workshop, you will create a Verilog RISC-V CPU from scratch, and you will modify this CPU to be suitable for different applications. You will learn and use modern techniques, using Transaction-Level Verilog to generate and modify your Verilog code more reliably, in far less time. You will discover how concepts like pipelining and hazards can be incorporated easily using timing-abstract design principles. All labs will be completed online in the Makerchip.com IDE for open-source circuit design. The skills you learn will be applicable far beyond CPU design.
Outline of Topics to be Covered: Digital logic using TL-Verilog and Makerchip – combinational logic – sequential logic – pipelined logic – validity – a calculator circuit Basic RISC-V CPU microarchitecture – single-cycle CPU microarchitecture – testbench, test program, and lab setup for your CPU – fetch, decode, and execute logic for RISC-V subset – control flow logic Pipelined RISC-V subset CPU microarchitecture – simple pipelining of the CPU – hazards and PC redirects Completing the RISC-V CPU – data memory and load/store – remaining RISC-V (RV32I) instructions
Course Format: – self paced, on demand course, providing attendees a flexible schedule – access to content for 30 days – pre-scheduled live Zoom and chat sessions with instructors during the 30 day access period – offline chat available with instructors during the entire 30 day access period (reply within 24 hours).
Target Audience: Engineers interested in a career in digital logic design or adjacent disciplines, including experienced engineers looking to modernize their skill set. Prerequisites: An engineering education and basic understanding of digital logic. (Verilog knowledge is not a prerequisite.)
Benefits of Attending: – Develop a solidified understanding of pipelined CPU design through hands-on labs. – Acquire knowledge of advanced digital circuit design methodology. – Gain exposure to an open-source design ecosystem. Speaker Bio: Steve Hoover is the founder of Redwood EDA, an early-stage startup focused on advanced silicon design methodology and tools. Steve is a former logic design lead for DEC, Compaq, and Intel and has extensive experience designing high-performance server CPUs and network switches.
Social Media Profile: System Requirements: All resources are free and online; no download or installation required.
We will use Slack, Zoom, GitHub Classroom, and Makerchip.com.
HPEC is the largest computing conference in New England and is the premier conference in the world on the convergence of High Performance and Embedded Computing. We are passionate about performance. Our community is interested in computing hardware, software, systems and applications where performance matters. We welcome experts and people who are new to the field.
Electronic Reliability Tutorial Fall Series – 2021
Electronic Reliability Series 3:
How to use Simulation and Modeling techniques to Improve Reliability
Electronics perform critical functions in every major industry vertical, whether in automotive, aerospace, consumer, medical or industrial segments. With the advent of newer technologies (both at the component and material levels), shrinkage of feature sizes, more stringent environments and sophisticated power requirements, electronics face increasing reliability risks. Supply chain trends have changed over the years from a vertically integrated model to a more geographically diverse supply chain. All these trends have increased reliability risks for companies. However, the cost of reliability assurance activities is often a fraction of the cost of failure, with compounding benefits from conducting these activities early in the design process.
This set of three tutorials will highlight how simulation and modeling can be used to optimize the design, gain assurance of passing qualification tests, and mitigate reliability issues early in the design process.
|Track II – Electronic Reliability Series 3 |
How to use Simulation and Modeling techniques to Improve Reliability
|1. Solder Alloys and Modeling Solder Reliabilities for Electronic Assemblies||Member: $80 |
|One day : 2 hours||Oct 7th @ 11am||Dr. Nathan Blattau|
|2. Printed Circuit Board Level Reliability Testing – Leveraging Testing, Failure Analysis, and Simulation to Improve Reliability||Member: $80 |
|One day : 2 hours||Oct 14th @ 11am||Michael Blattau & Nick Kirsch|
|3. Simulation Techniques to Evaluate ELK Stress During Chip Attach Process and Mitigate Failures||Member: $80 |
|One day : 2 hours||Oct 21 @ 11am||Dr. Gil Sharon & Tyler Ferris|
- Solder Alloys and Modeling Solder Reliability for Electronic Assemblies
Decision date to run Tutorial 1: Thursday, September 30, 2021
Duration: 2 hours
Abstract: Solder provides the structural and electrical connection between a printed wiring board (PWB) and electrical components. Solder is the most common material used for assembling electronics. However, while most materials only experience elastic deformation during use, solder is also one of the few structural materials that is expected to also undergo significant inelastic deformation during its lifetime.
Both elastic and inelastic deformation damages solder, causing the solder joints to fail, and consequentially the printed circuit assembly to fail. Predicting when the solder joint fails is critical when using solder in harsh use environments. These harsh environments have loads that can come in several forms (i.e., drop/shock, vibration, temperature cycling).
While vibration causes high cycle fatigue of solder, most solder fatigue failures in electronics are thermo-mechanically driven due to temperature cycling which causes significant deformations and stresses due to coefficient of thermal expansion (CTE) mismatches between the PWB and components. To predict solder failure, a damage model must be used that relates deformation of the solder to cycles to printed circuit board assembly failure.
In this tutorial, we will discuss material characterization of various solder alloys, predictive solder fatigue damage models using a physics-of-failure approach (PoF) for printed circuit board assemblies and how to develop damage models using simulation and testing.
Target audience: Engineers involved in the design, simulation and modeling, manufacturing and/or reliability of complex printed circuit board assemblies.
Benefits of attending
- Learn about different solder alloys and their failure mechanisms
- Characterizing solder material properties for simulation and modeling
- Methods for predicting reliability of electronic assemblies
Keywords/Hashtags: Electronic reliability, solder alloy, solder failure mechanisms, printed circuit board, electronic packaging, reliability physics, characterization, simulation and modeling
Bio: Dr. Nathan Blattau
Dr. Nathan Blattau, Distinguished Engineer at Ansys, has been involved in the simulation and reliability of electronic equipment for over twenty years. Prior to joining Ansys, Dr. Blattau was the Vice President and Chief Scientist of DfR Solutions. He holds two patents and has authored over 20 papers and has presented on a wide variety of reliability issues within the electronics industry. His specialties include best practices in design for reliability, robustness of Pb-free, failure analysis, accelerated test plan development, nonlinear finite element analysis, and solder joint reliability. Dr. Blattau holds a Ph.D. in Mechanical Engineering, an M.S. in Mechanical Engineering, and a B.S. in Civil Engineering from the University of Maryland.
2. Printed Circuit Board Level Reliability Testing – Leveraging Testing, Failure Analysis, and Simulation to Improve Reliability
Decision date to run Tutorial 2: Thursday, October 7, 2021
Duration: 2 hours
Abstract: Board Level Reliability Testing (BLRT) encompasses a range of environmental stress tests that evaluate the robustness of a semiconductor package once soldered to a printed circuit board (PCB). Solder joint reliability under thermal and mechanical loads has been the focus of BLRT programs, though increasingly other failure modes have also been identified for testing under these programs. While standards from organizations, such as JEDEC JEP150 and AEC Q104 (for automotive), provide guidance for BLRT testing, there is often ambiguity around test coupon design, test conditions, test duration, and failure criteria. This ambiguity can cause confusion, delay, and dissatisfaction up and down the supply chain.
Additionally, finite element modeling (FEM) is often underutilized in BLRT programs. Proactive simulation can be a helpful tool to design for reliability and improve overall BLRT robustness. This tutorial will cover tips for designing an appropriate BLRT program. This includes best practices in BLRT risk assessment, test coupon design, and experimental procedures. It will also review how to leverage simulation to improve BLRT design and performance.
Target audience: Engineers involved in the design, prototyping, qualification, or end use of new electronic package designs
Benefits of attending
- Learn about common failure modes and mechanisms of electronic package assemblies experienced and tested for in Printed Circuit Board Reliability Testing
- Learn about best practices for designing and conducting a board level reliability test program (BLRT)
- Learn how to use simulation to predict qualification test performance and reduce design cycles
Keywords/Hashtags: Electronic reliability, printed circuit board, failure modes and mechanisms, electronic packaging, Finite Element Modeling (FEM), Finite Element Analysis (FEA), solder joint reliability, Board Level Reliability Testing (BLRT), QFN, BGA, qualification testing.
Bio: Michael Blattau & Nick Kirsch
Michael Blattau is a Senior Consulting Engineer at Ansys with expertise in mechanical packaging of electronics. Prior to working for Ansys he was a Design Engineering Supervisor for over a decade with an embedded computer manufacturer. Michael brings significant expertise in electronics enclosure design, PCB layout, and FEA simulation and has a M.S., Electronic Packaging.
Nick Kirsch (MBA, PMP) leads the modeling and simulation team for ANSYS Reliability Engineering Services. He has a 9-year background as a project manager and engineer working with US Government and private sector clients to improve product performance, resolve manufacturing problems, manage complex testing programs, and provide expert analysis and guidance at all stages of the product development process. At ANSYS, his work focuses on validating and improving the mechanical performance of electronics systems through testing and FEA reliability simulations.
3. Simulation Techniques to Evaluate ELK Stress During Chip Attach Process and Mitigate Failures
Decision date to run Tutorial 3: Thursday, October 14, 2021
Duration: 2 hours
Abstract: Electronic component manufacturing requires a technology to connect a silicon die to a circuit. A popular method to do so is to flip the die and solder it using C4 bumps to a substrate. The substrate is then finished into a component. A major concern for flip chip technology nsion of the silicon die (2-3 ppm/°C) and the substrate (8-15 ppm/°C). The stress in the extreme low-k layers (ELK Stress) causes a brittle fracture).
This workshop is a hands-on tutorial on completing a simulation for this failure mode. The tutorial includes example files, analysis settings and best-known methods. The workshop will rely on the use of Ansys Sherlock, Ansys Mechanical and Ansys SpaceClaim inside the Ansys Workbench environment.
Target audience: Flip chip component designers and integrators, assembly bumping designers and manufacturers, chip attach, packaging and assembly engineers
Benefits of attending
- How to prevent flip Chip packaging and assembly issues
- Prevent ELK cracking problems before design
- Using simulation techniques to drive design for manufacturing (DfM)
Keywords/Hashtags: ELK cracking, white bumps, copper pillar, Electronics reliability, electronic packaging and assembly, reliability physics, Simulation and Modeling
Bio: Dr. Gil Sharon & Tyler Ferris
Dr. Sharon is a diverse industry expert with research specialties including mechanical reliability of electronic systems and characterization; embedded components failure analysis and particle beam accelerator mechanical fatigue; multidisciplinary reliability of complex electromechanical systems; characterization and modeling of material behavior; mechanical performance of flip chip packages; and Physics of Failure of electromechanical and MEMS systems. In addition to his responsibilities at ANSYS – DfR, Dr. Sharon serves as an adjunct faculty member at the University of Maryland.
Tyler Ferris is a Senior Consulting Engineer at Ansys and is an expert in the use of reliability physics, finite element analysis and hands-on laboratory failure analysis. Tyler has consulted with customers in the aerospace, automotive, industrial controls, data center industries and more, to evaluate system, PCBA and component-level failure risks and mitigation strategies.
Digital Signal Processing (DSP) for Software Radio
Course Start Date: Thursday, October 7, 2021, Videos released weekly 2×1.5 hours
Workshops: Tuesdays, October 12, 19, 26, November 2, 9
IEEE Member Fee: $190.00
Non-Member Fee: $210.00
Decision to run/cancel course: Thursday, September 30, 2021
Speaker: Dan Boschen
New Format Combining Live Workshops with Pre-recorded Video
This is a hands-on course providing pre-recorded lectures that students can watch on their own schedule and an unlimited number of times prior to live Q&A/Workshop sessions with the instructor. Ten 1.5 hour videos released 2 per week while the course is in session will be available for up to two months after the conclusion of the course.
This course builds on the IEEE course “DSP for Wireless Communications” also taught by Dan Boschen, further detailing digital signal processing most applicable to practical real-world problems and applications in radio communication systems. Students need not have taken the prior course if they are familiar with fundamental DSP concepts such as the Laplace and Z transform and basic digital filter design principles.
This course brings together core DSP concepts to address signal processing challenges encountered in radios and modems for modern wireless communications. Specific areas covered include carrier and timing recovery, equalization, automatic gain control, and considerations to mitigate the effects of RF and channel distortions such as multipath, phase noise and amplitude/phase offsets.
Dan builds an intuitive understanding of the underlying mathematics through the use of graphics, visual demonstrations, and real-world applications for mixed signal (analog/digital) modern transceivers. This course is applicable to DSP algorithm development with a focus on meeting practical hardware development challenges, rather than a tutorial on implementations with DSP processors.
Now with Jupyter Notebooks!
This long-running IEEE Course has been updated to
include Jupyter Notebooks which incorporates graphics together with Python simulation code to provide a “take-it-with-you” interactive user experience. No knowledge of Python is required but the notebooks will provide a basic framework for proceeding with further signal processing development using that tools for those that have interest in doing so.
This course will not be teaching Python, but using it for demonstration. A more detailed course on Python itself is covered in a separate IEEE Course routinely taught by Dan titled “Python Applications for Digital Design and Signal Processing”.
All set-up information for installation of all tools used will be provided prior to the start of class.
All engineers involved in or interested in signal processing for wireless communications. Students should have either taken the earlier course “DSP for Wireless Communications” or have been sufficiently exposed to basic signal processing concepts such as Fourier, Laplace, and Z-transforms, Digital filter (FIR/IIR) structures, and representation of complex digital and analog signals in the time and frequency domains. Please contact Dan at email@example.com if you are uncertain about your background or if you would like more information on the course.
Benefits of Attending/ Goals of Course:
Attendees will gain a strong intuitive understanding of the practical and common signal processing implementations found in modern radio and modem architectures and be able to apply these concepts directly to communications system design.
Topics / Schedule:
Class 1: DSP Review, Radio Architectures, Digital Mapping, Pulse Shaping, Eye Diagrams
Class 2: ADC Receiver, CORDIC Rotator, Digital Down Converters, Numerically Controlled Oscillators
Class 3: Digital Control Loops; Output Power Control, Automatic Gain Control
Class 4: Digital Control Loops; Carrier and Timing Recovery, Sigma Delta Converters
Class 5: RF Signal Impairments, Equalization and Compensation, Linear Feedback Shift Registers
Dan Boschen has a MS in Communications and Signal Processing from Northeastern University, with over 25 years of experience in system and hardware design for radio transceivers and modems. He has held various positions at Signal Technologies, MITRE, Airvana and Hittite Microwave designing and developing transceiver hardware from baseband to antenna for wireless communications systems and has taught courses on DSP to international audiences for over 15 years. Dan is a contributor to Signal Processing Stack Exchange https://dsp.stackexchange.com/, and is currently at Microchip (formerly Microsemi and Symmetricom) leading design efforts for advanced frequency and time solutions.
For more background information, please view Dan’s Linked-In page at: http://www.linkedin.com/in/danboschen
IEEE Boston Section recognized for Excellence in Membership Recruitment Performance
IEEE Boston Section was founded Feb 13, 1903, and serves more than 8,500 members of the IEEE. There are 29 chapters and affinity groups covering topics of interest from Aerospace & Electronic Systems, to Entrepreneur Network to Women in Engineering to Young Professionals. The chapters and affinity groups organize more than 100 meetings a year. In addition to the IEEE organization activities, the Boston Section organizes and sponsors up to seven conferences in any given year, as well as more than 45 short courses. The Boston Section publishes a bi-weekly newsletter and, currently, a monthly Digital Reflector newspaper included in IEEE membership.
The IEEE Boston Section also offers social programs such as the section annual meeting, Milestone events, and other non-technical professional activities to round out the local events. The Section also hosts one of the largest and longest running entrepreneurial support groups in IEEE.
More than 150 volunteers help create and coordinate events throughout the year.