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Topic 4: Bit/cycle accurate modelling and analysis using the design examples and simulation packages
Speaker’s Bio:
Dan Boschen has a MS in Communications and Signal Processing from Northeastern University, with over 25 years of experience in system and hardware design for radio transceivers and modems. He has held various positions at Signal Technologies, MITRE, Airvana and Hittite Microwave designing and developing transceiver hardware from baseband to antenna for wireless communications systems and has taught courses on DSP to international audiences for over 15 years. Dan is a contributor to Signal Processing Stack Exchange https://dsp.stackexchange.com/, and is currently at Microchip (formerly Microsemi and Symmetricom) leading design efforts for advanced frequency and time solutions. For more background information, please view Dan’s Linked-In page. Registration is open through the last live workshop date. Live workshops are recorded for later use.IEEE Boston Course Information (hosted by MITRE Corporation)
This is a Hybrid Course
Lecturer: Kendall Farnham (Dartmouth College)
Time: 6:00PM – 7:30PM
Course Overview:
Field-programmable gate arrays (FPGAs) are versatile integrated circuits that offer a flexible and reconfigurable hardware platform for implementing custom digital circuits, particularly in applications requiring specialized architectures. Unlike application-specific integrated circuits (ASICs), FPGAs can be programmed and reprogrammed after manufacturing using hardware description languages (HDLs), enabling rapid prototyping and iterative design processes. FPGAs can be found in telecommunications, signal processing, aerospace, and other scenarios demanding high-performance computing, parallel processing, low-latency data processing, and real-time operations. The newest trends include integrating FPGAs with systems on chip (SoCs) for implementing low-latency machine learning (ML) and artificial intelligence.
This Advanced Digital Design course is an intensive program designed to build upon foundational concepts in digital logic design and equip students with the skills needed to implement robust high-speed ML algorithms on an FPGA. Through a combination of theoretical lectures, hands-on exercises, and practical projects, students will explore advanced FPGA topics encompassing architectural considerations, signal integrity, timing analysis, and optimization techniques to achieve reliable and efficient high-speed designs. Additionally, this course will encourage students to explore current research papers and real-world industry applications to foster a deeper appreciation for advancements in state-of-the-art FPGA design.
Target audience: Students and professionals with a base knowledge of FPGA design looking to advance hardware design skills for developing complex customized circuits for efficient implementation of ML.
Benefits of attending:
- Valuable professional development creating skills that lead to job offers
- Reinforce and expand knowledge of VHDL and FPGA-specific design methodology.
- Develop skills for implementing high-speed, robust, reliable circuits on FPGAs.
- Gain understanding of real-world industry applications of FPGAs and SoCs.
Course Objectives: By the end of this course, students will possess the expertise needed to tackle complex high-speed hardware design challenges using FPGAs. They will be well-prepared to contribute to cutting-edge research, industry projects, and advancements in areas such as telecommunications, data centers, embedded systems, and high-performance computing.
Prerequisites:
- Understanding of digital logic design principles and methodology (e.g., Boolean algebra, finite state machines, data path elements)
- Familiarity with VHDL programming (or Verilog)
- Experience with FPGA development boards and tools (e.g., Vivado)
Speaker Bio:
Kendall Farnham (Dartmouth College)
Kendall Farnham is a PhD candidate in Dr. Ryan Halter’s bioimpedance lab at the Thayer School of Engineering, Dartmouth College. She has 10+ years of experience in the electrical and computer engineering (ECE) field and 5+ years of teaching and mentoring experience, having held several leadership positions within academia and industry. She received her bachelor’s degree in ECE in 2014, worked in the defense industry as a software engineer for 4 years where she discovered her passion for research, and returned to school to expand her education to include hardware design for space medicine applications. Specifically, she is interested in FPGA-based biomedical device design, currently working to develop space-compatible technologies that use impedance to monitor and detect physiological effects of space travel. Her expertise includes high-performance FPGA-based digital system design, analog circuit design, multi-modal imaging algorithms, and system integration.
Detailed Course Outline:
- Review of Digital Logic Design and FPGA Programming
- Boolean algebra, combinational and sequential circuits, finite state machines
- FPGA, SoC, and SoM architectures and toolchains
- VHDL programming techniques and design methodology
- Writing effective testbenches, RTL simulation in Vivado
- Introduction to ML algorithms and FPGA-specific optimization strategies
- High-throughput Communication on FPGAs
- Pipelining and parallelism for high-speed designs
- Synchronous vs. asynchronous communication protocols (SPI, SCI, UART, LVDS, I2C, PCIe, USB, Ethernet, etc.)
- Compare hardware/software/firmware implementations of ML: throughput speeds, resource utilization, and latency
- Methods used to achieve ultra-high sampling rates (>> system clock, GS/s range)
- Utilizing advanced IP cores and IO buffers for high-speed interfaces and data storage
- Advanced FPGA Techniques for High-speed Systems
- Clock domain crossing verification and synchronization techniques
- Resource utilization, critical path identification, and optimization strategies
- Timing constraints, static and dynamic timing analysis
- Signal integrity analysis
- High-Speed Design Verification and Testing
- Simulation-based verification techniques, advanced debugging, and waveform analysis
- Post-layout verification and back-annotation
- Test and validation strategies for high-speed designs
- Utilizing debug cores for real-time logic analysis
- Machine Learning on FPGAs
- Algorithm validation and verification in software
- Compare capabilities and implementation strategies of ML on FPGAs, SoCs, and SoMs
- Optimization strategies for efficient ML implementation in hardware (e.g., convolution)
- Digital Systems in Industry
- Techniques and best practices for scalable, reusable, reliable, and robust FPGA design
- Board-level considerations for high-speed signals: PCB layout guidelines, power distribution and decoupling, transmission line theory and termination techniques
- Emerging trends for FPGA-based digital signal processing (DSP) applications
REGISTRATION FEES:
Early Rate ends on September 3, 2024
IEEE Members Early Rate: $120.00
IEEE Non-Members Early Rate: $250.00
Rates after September 3, 2024:
IEEE Members: $140.00
IEEE Non-Members: $300.00
Decision to run the course is: Monday, September 9, 2024
We can offer Continuing Education Units (CEU) and Professional Development Hours (PDH), if requested. A small fee may apply for the credits.
Consultants’ Network
Free Dinner starts at 6:00 PM
Meeting starts at 7:00 PM – On-site and Zoom
Members in good standing are encouraged to attend. If you are unable to attend, then we will also be on Zoom.
Your registration confirmation email contains the Zoom details.
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For CNET members:
- Professional interactions with peers in a supporting environment.
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- Opportunity to give presentations and hone speaking effectiveness.
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For engineers interested in becoming consultants:
- Basic information on consulting practice requirements.
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For enquirers on CNET services:
- Convenient access to local consultants with multi-disciplinary expertise.
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- Direct, easy connection with consultants over the CNET web page.
- Dealing with consultants with multi-year experience validated by IEEE.
Join us!
Microwave Theory & Technique Society
After work social networking event for Boston Young Professional Microwave Theory and Technology Society members or those who work in the field and are looking to make more professional connections. We encourage bringing business cards for exchanging contact information!
Organizers will provide some pizza and appetizers based on expected head count.
Event information can be found at: https://events.vtools.ieee.org/m/429911
Our website link: https://r1.ieee.org/mtts-boston/2024/08/07/young-professionals-networking-social-17-september-2024/
Microwave Theory & Techniques Society
After work social networking event for Boston Young Professional Microwave Theory and Technology Society members or those who work in the field and are looking to make more professional connections. We encourage bringing business cards for exchanging contact information!
Organizers will provide some pizza and appetizers based on expected head count.
Event information and registration can be found at: https://events.vtools.ieee.org/m/429911
Our website link: https://r1.ieee.org/mtts-boston/2024/08/07/young-professionals-networking-social-17-september-2024/
IEEE Boston Section recognized for Excellence in Membership Recruitment Performance
The IEEE Boston Section was founded Feb 13, 1903, and serves more than 8,500 local members. We have 29 chapters and affinity groups covering topics of interest from Aerospace & Electronic Systems, to Entrepreneur Network to Women in Engineering to Young Professionals. Our chapters and affinity groups organize more than 100 meetings a year and up to seven conferences in any given year, as well as more than 45 short courses. We publish a bi-weekly newsletter and, currently, a monthly Digital Reflector newsletter included in your IEEE membership.
IEEE Boston Section offers social programs such as the section annual meeting, Milestone events, and other non-technical professional activities to round out the local events. We proudly host one of the largest and longest running entrepreneurial support groups in IEEE.
More than 150 volunteers help create and coordinate events throughout the year.
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