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Tom Meuse of Thermo Fisher Scientific
As device technologies evolve and continue to shrink, manufacturing methods are also being stressed, which can impact yields due to ESD performance. ESD test standards are continuing to evolve as well to meet these changes. However as complex devices such as 3D packing with 1000s of Die to Die interconnects become more widely used, this is challenging the “standard” way ESD testing is performed. Another point of interest for system level testing, is call for a Direct Pin Injection test method. Although the most widely used system level testing standard, IEC 61000-4-2 standard recommends not performing testing on pins of a connector, many manufacturers are being forced to perform this test. We’ll discuss the Industry Councils on ESD Target Levels approaches to this testing requirement. Tom Meuse is an Applications/Product/Technology Engineer for the Compliance Test Solutions division of Thermo Fisher Scientific, which is located in Tewksbury MA, USA. He is responsible for the Thermo Scientific ESD and Latch-up test system operations and future product research. Tom is a member of the ESD Association Device Testing (WG-5.x) committee, chair of the ESDA’s WG14 System Level working group and a member of the JEDEC JC-14.1 Committee on Reliability Test Methods. He’s also a member of the Joint ESDA/JEDEC Device Testing work group and a contributing member to the Industry Council on ESD Target Levels. In addition, he’s also a Board of Directors member on both the National and the Northeast Chapter of the ESD Association. During Tom’s 40 plus year career, which began with KeyTek Instruments, he worked on Surge and ESD simulator designs, in both an engineering capacity and as the project manager on both system level and device level testers. He’s provided numerous technical seminars focusing on ESD/Latch-up testing and Standards Evolution and has authored and co-authored numerous papers on topics relating to ESD device level testing and ESD system design. Agenda
5:30 PM Pizza, salad, soda, and Networking 6:00 PM Technical Presentation 6:45 PM Questions and Answers 7:00 PM Adjournment The meeting is open to all. You do not need to belong to the IEEE to attend this event; however, we welcome your consideration of IEEE membership as a career enhancing technical affiliation. There is no cost to register or attend, but registration is required. Registration: https://events.vtools.ieee.org/m/427623IEEE Boston/Providence/New Hampshire Reliability Chapter
As device technologies evolve and continue to shrink, manufacturing methods are also being stressed, which can impact yields due to ESD performance. ESD test standards are continuing to evolve as well to meet these changes. However as complex devices such as 3D packing with 1000s of Die to Die interconnects become more widely used, this is challenging the “standard” way ESD testing is performed.
Another point of interest for system level testing, is call for a Direct Pin Injection test method. Although the most widely used system level testing standard, IEC 61000-4-2 standard recommends not performing testing on pins of a connector, many manufacturers are being forced to perform this test. We’ll discuss the Industry Councils on ESD Target Levels approaches to this testing requirement.
Tom Meuse of Thermo Fisher Scientific
As device technologies evolve and continue to shrink, manufacturing methods are also being stressed, which can impact yields due to ESD performance. ESD test standards are continuing to evolve as well to meet these changes. However as complex devices such as 3D packing with 1000s of Die to Die interconnects become more widely used, this is challenging the “standard” way ESD testing is performed.
Another point of interest for system level testing, is call for a Direct Pin Injection test method. Although the most widely used system level testing standard, IEC 61000-4-2 standard recommends not performing testing on pins of a connector, many manufacturers are being forced to perform this test. We’ll discuss the Industry Councils on ESD Target Levels approaches to this testing requirement.
Tom Meuse is an Applications/Product/Technology Engineer for the Compliance Test Solutions division of Thermo Fisher Scientific, which is located in Tewksbury MA, USA. He is responsible for the Thermo Scientific ESD and Latch-up test system operations and future product research. Tom is a member of the ESD Association Device Testing (WG-5.x) committee, chair of the ESDA’s WG14 System Level working group and a member of the JEDEC JC-14.1 Committee on Reliability Test Methods. He’s also a member of the Joint ESDA/JEDEC Device Testing work group and a contributing member to the Industry Council on ESD Target Levels. In addition, he’s also a Board of Directors member on both the National and the Northeast Chapter of the ESD Association.
During Tom’s 40 plus year career, which began with KeyTek Instruments, he worked on Surge and ESD simulator designs, in both an engineering capacity and as the project manager on both system level and device level testers. He’s provided numerous technical seminars focusing on ESD/Latch-up testing and Standards Evolution and has authored and co-authored numerous papers on topics relating to ESD device level testing and ESD system design.
Agenda
5:30 PM Pizza, salad, soda, and Networking
6:00 PM Technical Presentation
6:45 PM Questions and Answers
7:00 PM Adjournment
The meeting is open to all. You do not need to belong to the IEEE to attend this event; however, we welcome your consideration of IEEE membership as a career enhancing technical affiliation.
There is no cost to register or attend, but registration is required.
Registration: https://events.vtools.ieee.org/m/427623
COURSE DESCRIPTION
Course Kick-off / Orientation Thursday, October 10, 6:00PM – 6:30PM.
Live Workshops: 6:00PM – 7:30PM, Thursdays, October 17, 24, 31, November 7, 14, 2024
Registration is open through the last live workshop date. Live workshops are recorded for later use.
Attendees will have access to the recorded session and exercises for two months (until February 14, 2025) after the live session ends!
Speaker: Dan Boschen
IEEE Member Fee (by October 8): $190.00
IEEE Member Fee (after October 8): $285.00
IEEE Non-Member Fee (by October 8): $210.00
IEEE Non-Member Fee (after October 8) $315.00
Decision to run/cancel course: Friday, October 4, 2024
COURSE DESCRIPTION
New Format Combining Live Workshops with Pre-recorded Video
This is a hands-on course providing pre-recorded lectures that students can watch on their own schedule and an unlimited number of times prior to live Q&A/Workshop sessions with the instructor. Ten 1.5 hour videos released 2 per week while the course is in session will be available for up to two months after the conclusion of the course.
Course Summary
This course is a fresh view of the fundamental and practical concepts of digital signal processing applicable to the design of mixed signal design with A/D conversion, digital filters, operations with the FFT, and multi-rate signal processing. This course will build an intuitive understanding of the underlying mathematics through the use of graphics, visual demonstrations, and applications in GPS and mixed signal (analog/digital) modern transceivers. This course is applicable to DSP algorithm development with a focus on meeting practical hardware development challenges in both the analog and digital domains, and not a tutorial on working with specific DSP processor hardware.
Now with Jupyter Notebooks!
This long-running IEEE Course has been updated to include Jupyter Notebooks which incorporates graphics together with Python simulation code to provide a “take-it-with-you” interactive user experience. No knowledge of Python is required but the notebooks will provide a basic framework for proceeding with further signal processing development using that tools for those that have interest in doing so.
This course will not be teaching Python, but using it for demonstration. A more detailed course on Python itself is covered in a separate IEEE Course “Python Applications for Digital Design and Signal Processing”.
Students will be encouraged but not required to load all the Python tools needed, and all set-up information for installation will be provided prior to the start of class.
Target Audience:
All engineers involved in or interested in signal processing applications. Engineers with significant experience with DSP will also appreciate this opportunity for an in-depth review of the fundamental DSP concepts from a different perspective than that given in a traditional introductory DSP course.
Benefits of Attending/ Goals of Course:
Attendees will build a stronger intuitive understanding of the fundamental signal processing concepts involved with digital filtering and mixed signal analog and digital design. With this, attendees will be able to implement more creative and efficient signal processing architectures in both the analog and digital domains. The knowledge gained from this course will have immediate practical value for any work in the signal processing field.
Topics / Schedule:
Pre-recorded lectures: (3 hours each) will be distributed Friday prior to each week’s workshop dates. Workshop/Q&A Sessions are 6 – 7:30PM on the dates listed below.
Kick-off / Orientation: Thursday, October 10, 2024
Class 1: October 17, 2024: Correlation, Fourier Transform, Laplace Transform
Class 2: October 24, 2024: Sampling and A/D Conversion, Z –transform, D/A Conversion
Class 3: October 31, 2024: IIR and FIR Digital filters, Direct Fourier Transform
Class 4: November 7, 2024: May Windowing, Digital Filter Design, Fixed Point vs Floating Point
Class 5: November 14, 2024: Fast Fourier Transform, Multi-rate Signal Processing, Multi-rate Filters
Speaker’s Bio:
Dan Boschen has a MS in Communications and Signal Processing from Northeastern University, with over 25 years of experience in system and hardware design for radio transceivers and modems. He has held various positions at Signal Technologies, MITRE, Airvana and Hittite Microwave designing and developing transceiver hardware from baseband to antenna for wireless communications systems. Dan is currently at Microchip (formerly Microsemi and Symmetricom) leading design efforts for advanced frequency and time solutions.
For more background information, please view Dan’s Linked-In page at: http://www.linkedin.com/in/danboschen
Registration is open through the last live workshop date. Live workshops are recorded for later use.
COURSE DESCRIPTION
Course Kick-off / Orientation Thursday, October 10, 6:00PM – 6:30PM.
Live Workshops: 6:00PM – 7:30PM, Thursdays, October 17, 24, 31, November 7, 14, 2024
Registration is open through the last live workshop date. Live workshops are recorded for later use.
Attendees will have access to the recorded session and exercises for two months (until February 14, 2025) after the live session ends!
Speaker: Dan Boschen
IEEE Member Fee (by October 8): $190.00
IEEE Member Fee (after October 8): $285.00
IEEE Non-Member Fee (by October 8): $210.00
IEEE Non-Member Fee (after October 8) $315.00
Decision to run/cancel course: Friday, October 4, 2024
COURSE DESCRIPTION
New Format Combining Live Workshops with Pre-recorded Video
This is a hands-on course providing pre-recorded lectures that students can watch on their own schedule and an unlimited number of times prior to live Q&A/Workshop sessions with the instructor. Ten 1.5 hour videos released 2 per week while the course is in session will be available for up to two months after the conclusion of the course.
Course Summary
This course is a fresh view of the fundamental and practical concepts of digital signal processing applicable to the design of mixed signal design with A/D conversion, digital filters, operations with the FFT, and multi-rate signal processing. This course will build an intuitive understanding of the underlying mathematics through the use of graphics, visual demonstrations, and applications in GPS and mixed signal (analog/digital) modern transceivers. This course is applicable to DSP algorithm development with a focus on meeting practical hardware development challenges in both the analog and digital domains, and not a tutorial on working with specific DSP processor hardware.
Now with Jupyter Notebooks!
This long-running IEEE Course has been updated to include Jupyter Notebooks which incorporates graphics together with Python simulation code to provide a “take-it-with-you” interactive user experience. No knowledge of Python is required but the notebooks will provide a basic framework for proceeding with further signal processing development using that tools for those that have interest in doing so.
This course will not be teaching Python, but using it for demonstration. A more detailed course on Python itself is covered in a separate IEEE Course “Python Applications for Digital Design and Signal Processing”.
Students will be encouraged but not required to load all the Python tools needed, and all set-up information for installation will be provided prior to the start of class.
Target Audience:
All engineers involved in or interested in signal processing applications. Engineers with significant experience with DSP will also appreciate this opportunity for an in-depth review of the fundamental DSP concepts from a different perspective than that given in a traditional introductory DSP course.
Benefits of Attending/ Goals of Course:
Attendees will build a stronger intuitive understanding of the fundamental signal processing concepts involved with digital filtering and mixed signal analog and digital design. With this, attendees will be able to implement more creative and efficient signal processing architectures in both the analog and digital domains. The knowledge gained from this course will have immediate practical value for any work in the signal processing field.
Topics / Schedule:
Pre-recorded lectures: (3 hours each) will be distributed Friday prior to each week’s workshop dates. Workshop/Q&A Sessions are 6 – 7:30PM on the dates listed below.
Kick-off / Orientation: Thursday, October 10, 2024
Class 1: October 17, 2024: Correlation, Fourier Transform, Laplace Transform
Class 2: October 24, 2024: Sampling and A/D Conversion, Z –transform, D/A Conversion
Class 3: October 31, 2024: IIR and FIR Digital filters, Direct Fourier Transform
Class 4: November 7, 2024: May Windowing, Digital Filter Design, Fixed Point vs Floating Point
Class 5: November 14, 2024: Fast Fourier Transform, Multi-rate Signal Processing, Multi-rate Filters
Speaker’s Bio:
Dan Boschen has a MS in Communications and Signal Processing from Northeastern University, with over 25 years of experience in system and hardware design for radio transceivers and modems. He has held various positions at Signal Technologies, MITRE, Airvana and Hittite Microwave designing and developing transceiver hardware from baseband to antenna for wireless communications systems. Dan is currently at Microchip (formerly Microsemi and Symmetricom) leading design efforts for advanced frequency and time solutions.
For more background information, please view Dan’s Linked-In page at: http://www.linkedin.com/in/danboschen
Registration is open through the last live workshop date. Live workshops are recorded for later use.
IEEE Boston Section recognized for Excellence in Membership Recruitment Performance
IEEE Boston Section was founded Feb 13, 1903, and serves more than 8,500 members of the IEEE. There are 29 chapters and affinity groups covering topics of interest from Aerospace & Electronic Systems, to Entrepreneur Network to Women in Engineering to Young Professionals. The chapters and affinity groups organize more than 100 meetings a year. In addition to the IEEE organization activities, the Boston Section organizes and sponsors up to seven conferences in any given year, as well as more than 45 short courses. The Boston Section publishes a bi-weekly newsletter and, currently, a monthly Digital Reflector newspaper included in IEEE membership.
The IEEE Boston Section also offers social programs such as the section annual meeting, Milestone events, and other non-technical professional activities to round out the local events. The Section also hosts one of the largest and longest running entrepreneurial support groups in IEEE.
More than 150 volunteers help create and coordinate events throughout the year.