Electronic Reliability Tutorial Series 3

October 14, 2021 @ 11:00 am – 1:00 pm America/New York Timezone

Electronic Reliability Tutorial Fall Series – 2021

Electronic Reliability Series 3:

Member:  $80.00

Non-Member:  $100.00



How to use Simulation and Modeling techniques to Improve Reliability

Electronics perform critical functions in every major industry vertical, whether in automotive, aerospace, consumer, medical or industrial segments.  With the advent of newer technologies (both at the component and material levels), shrinkage of feature sizes, more stringent environments and sophisticated power requirements, electronics face increasing reliability risks.  Supply chain trends have changed over the years from a vertically integrated model to a more geographically diverse supply chain.  All these trends have increased reliability risks for companies.  However, the cost of reliability assurance activities is often a fraction of the cost of failure, with compounding benefits from conducting these activities early in the design process.

This set of three tutorials will highlight how simulation and modeling can be used to optimize the design, gain assurance of passing qualification tests, and mitigate reliability issues early in the design process.

Tutorial Options Price Duration Date/Time Instructor
Track II – Electronic Reliability Series 3

How to use Simulation and Modeling techniques to Improve Reliability

1.       Solder Alloys and Modeling Solder Reliabilities for Electronic Assemblies Member:  $80

Non-Member: $100

One day : 2 hours Oct 7th @ 11am Dr. Nathan Blattau
2.       Printed Circuit Board Level Reliability Testing – Leveraging Testing, Failure Analysis, and Simulation to Improve Reliability Member:  $80

Non-Member: $100

One day : 2 hours Oct 14th @ 11am Michael Blattau & Nick Kirsch
3.       Simulation Techniques to Evaluate ELK Stress During Chip Attach Process and Mitigate Failures Member:  $80

Non-Member: $100

One day : 2 hours Oct 21 @ 11am Dr.  Gil Sharon & Tyler Ferris
  1. Solder Alloys and Modeling Solder Reliability for Electronic Assemblies

Decision date to run Tutorial 1:  Thursday, September 30, 2021

Duration: 2 hours

Abstract: Solder provides the structural and electrical connection between a printed wiring board (PWB) and electrical components.  Solder is the most common material used for assembling electronics. However, while most materials only experience elastic deformation during use, solder is also one of the few structural materials that is expected to also undergo significant inelastic deformation during its lifetime.

Both elastic and inelastic deformation damages solder, causing the solder joints to fail, and consequentially the printed circuit assembly to fail. Predicting when the solder joint fails is critical when using solder in harsh use environments.  These harsh environments have loads that can come in several forms (i.e., drop/shock, vibration, temperature cycling).

While vibration causes high cycle fatigue of solder, most solder fatigue failures in electronics are thermo-mechanically driven due to temperature cycling which causes significant deformations and stresses due to coefficient of thermal expansion (CTE) mismatches between the PWB and components. To predict solder failure, a damage model must be used that relates deformation of the solder to cycles to printed circuit board assembly failure.

In this tutorial, we will discuss material characterization of various solder alloys, predictive solder fatigue damage models using a physics-of-failure approach (PoF) for printed circuit board assemblies and how to develop damage models using simulation and testing.

Target audience:  Engineers involved in the design, simulation and modeling, manufacturing and/or reliability of complex printed circuit board assemblies.

Benefits of attending

  • Learn about different solder alloys and their failure mechanisms
  • Characterizing solder material properties for simulation and modeling
  • Methods for predicting reliability of electronic assemblies

Keywords/Hashtags: Electronic reliability, solder alloy, solder failure mechanisms, printed circuit board, electronic packaging, reliability physics, characterization, simulation and modeling

Bio: Dr. Nathan Blattau

Dr. Nathan Blattau, Distinguished Engineer at Ansys, has been involved in the simulation and reliability of electronic equipment for over twenty years.  Prior to joining Ansys, Dr. Blattau was the Vice President and Chief Scientist of DfR Solutions.  He holds two patents and has authored over 20 papers and has presented on a wide variety of reliability issues within the electronics industry.  His specialties include best practices in design for reliability, robustness of Pb-free, failure analysis, accelerated test plan development, nonlinear finite element analysis, and solder joint reliability. Dr. Blattau holds a Ph.D. in Mechanical Engineering, an M.S. in Mechanical Engineering, and a B.S. in Civil Engineering from the University of Maryland.

2.  Printed Circuit Board Level Reliability Testing – Leveraging Testing, Failure Analysis, and Simulation to Improve Reliability

Decision date to run Tutorial 2:  Thursday, October 7, 2021

Duration: 2 hours

Abstract: Board Level Reliability Testing (BLRT) encompasses a range of environmental stress tests that evaluate the robustness of a semiconductor package once soldered to a printed circuit board (PCB). Solder joint reliability under thermal and mechanical loads has been the focus of BLRT programs, though increasingly other failure modes have also been identified for testing under these programs. While standards from organizations, such as JEDEC JEP150 and AEC Q104 (for automotive), provide guidance for BLRT testing, there is often ambiguity around test coupon design, test conditions, test duration, and failure criteria. This ambiguity can cause confusion, delay, and dissatisfaction up and down the supply chain.

Additionally, finite element modeling (FEM) is often underutilized in BLRT programs. Proactive simulation can be a helpful tool to design for reliability and improve overall BLRT robustness. This tutorial will cover tips for designing an appropriate BLRT program. This includes best practices in BLRT risk assessment, test coupon design, and experimental procedures.  It will also review how to leverage simulation to improve BLRT design and performance.

Target audience:  Engineers involved in the design, prototyping, qualification, or end use of new electronic package designs

Benefits of attending

  • Learn about common failure modes and mechanisms of electronic package assemblies experienced and tested for in Printed Circuit Board Reliability Testing
  • Learn about best practices for designing and conducting a board level reliability test program (BLRT)
  • Learn how to use simulation to predict qualification test performance and reduce design cycles

Keywords/Hashtags: Electronic reliability, printed circuit board, failure modes and mechanisms, electronic packaging, Finite Element Modeling (FEM), Finite Element Analysis (FEA), solder joint reliability, Board Level Reliability Testing (BLRT), QFN, BGA, qualification testing.

Bio: Michael Blattau & Nick Kirsch

Michael Blattau is a Senior Consulting Engineer at Ansys with expertise in mechanical packaging of electronics.  Prior to working for Ansys he was a Design Engineering Supervisor for over a decade with an embedded computer manufacturer.  Michael brings significant expertise in electronics enclosure design, PCB layout, and FEA simulation and has a M.S., Electronic Packaging.

Nick Kirsch (MBA, PMP) leads the modeling and simulation team for ANSYS Reliability Engineering Services.  He has a 9-year background as a project manager and engineer working with US Government and private sector clients to improve product performance, resolve manufacturing problems, manage complex testing programs, and provide expert analysis and guidance at all stages of the product development process.  At ANSYS, his work focuses on validating and improving the mechanical performance of electronics systems through testing and FEA reliability simulations.

3.  Simulation Techniques to Evaluate ELK Stress During Chip Attach Process and Mitigate Failures

Decision date to run Tutorial 3:  Thursday, October 14, 2021

Duration: 2 hours

Abstract: Electronic component manufacturing requires a technology to connect a silicon die to a circuit. A popular method to do so is to flip the die and solder it using C4 bumps to a substrate. The substrate is then finished into a component. A major concern for flip chip technology nsion of the silicon die (2-3 ppm/°C) and the substrate (8-15 ppm/°C). The stress in the extreme low-k layers (ELK Stress) causes a brittle fracture).

This workshop is a hands-on tutorial on completing a simulation for this failure mode. The tutorial includes example files, analysis settings and best-known methods. The workshop will rely on the use of Ansys Sherlock, Ansys Mechanical and Ansys SpaceClaim inside the Ansys Workbench environment.

Target audience:  Flip chip component designers and integrators, assembly bumping designers and manufacturers, chip attach, packaging and assembly engineers

Benefits of attending

    • How to prevent flip Chip packaging and assembly issues
    • Prevent ELK cracking problems before design
    • Using simulation techniques to drive design for manufacturing (DfM)

Keywords/Hashtags: ELK cracking, white bumps, copper pillar, Electronics reliability, electronic packaging and assembly, reliability physics, Simulation and Modeling

Bio: Dr. Gil Sharon & Tyler Ferris

Dr. Sharon is a diverse industry expert with research specialties including mechanical reliability of electronic systems and characterization; embedded components failure analysis and particle beam accelerator mechanical fatigue; multidisciplinary reliability of complex electromechanical systems; characterization and modeling of material behavior; mechanical performance of flip chip packages; and Physics of Failure of electromechanical and MEMS systems. In addition to his responsibilities at ANSYS – DfR, Dr. Sharon serves as an adjunct faculty member at the University of Maryland.

Tyler Ferris is a Senior Consulting Engineer at Ansys and is an expert in the use of reliability physics, finite element analysis and hands-on laboratory failure analysis. Tyler has consulted with customers in the aerospace, automotive, industrial controls, data center industries and more, to evaluate system, PCBA and component-level failure risks and mitigation strategies.