Verilog 101: Verilog Foundations – Online Course

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You will have 90 days to access Verilog Foundations. The lab database is downloadable and yours to keep.

Speaker Bio:

Jay Tyer has been teaching Verilog, Timing Analysis and various EDA tools for 15 years. He has been working in the development of online classes for several years.

Course Description:

Verilog is IEEE standard 1364. It is a Hardware Description Language that is the corner stone of much of the simulation world. Verilog Foundations is a comprehensive introduction to the IEEE 1364 (Verilog). The Verilog Foundations class has a slightly different approach to learning Verilog than other methods. There is a lecture section for each main topic. This presents a basic foundation for the language. What makes Verilog Foundations exciting is the emphasis on labs/examples. There are nearly 100 labs/examples giving comprehensive “how to” examples of most Verilog language constructs. There are working solutions for each lab and the students can use the lab database for developing their own models later. The class is also self paced. All the work can be done independently by the engineers, at their own computer, and at their own pace.

There are self-grading quizzes for each chapter that allow the student to see if he/she is learning the material.

Course Objectives

The goals of this course are to make you familiar with developing a Verilog model, both behavioral and structural, using as much of the language as possible, and writing a verification test for that model.

TARGET AUDIENCE:

Hardware engineers. Verilog Foundations is good for the Verilog newbie or can be used as a good reference for the seasoned Verilog engineer.

PREREQUISITE:

Students must have a computer with internet access. The class is written in HTML so any browser with a Flash (version 6 or higher) player will work. If the free simulator is to be used then the computer must be a PC.

COURSE OUTLINE:

There are 12 lecture chapters in Verilog Foundations. They are:

  • Introduction
  • Foundations
  • Getting Started
  • Verilog Lexical Conventions
  • Data Types
  • Structural Modeling
  • User Defined Primitives
  • Behavioral Modeling
  • Memories
  • Operators
  • Modeling Timing Delays and Timing Checks
  • Synthesis Modeling

Course Fee Schedule: Registration is On-Going
IEEE Members $250
Non-members $300