SystemVerilog 101 (SV101): Design Constructs – Online Course

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You will have 90 days to access SystemVerilog 101 . The lab database is downloadable and yours to keep.

Speaker Bio:

Jay Tyer, a graduate of WPI, has been teaching Verilog, Timing Analysis and various EDA tools for 17 years. He has been working in the development of online classes for several years.

Course Description

SytemVerilog is an extensive set of language constructs to the IEEE 1364-2001 standard. It’s meant to aid in the creation and verification of models. There are two parts to the language extension. The first part covered by this class, is new design constructs. The second part of SystemVerilog is verification constructs, covered by SystemVerilog102.

There are over 100 labs/examples giving comprehensive “how to” examples of most SystemVerilog language constructs. There are working solutions for each lab and the students can use the lab database for developing their own models later. The class is also self paced. All the work can be done independently by the engineers, at their own computer, and at their own pace.

There are self-grading quizzes for each chapter that allow the student to see if he/she is learning the material.

Course Objectives

The goals of this course are to make you familiar with the new part of the language.

TARGET AUDIENCE:

Hardware engineers. SystemVerilog is the next stage in the evolution of Verilog. Every Verilog engineer will need to know this information.

PREREQUISITE:

Students must have a computer with Internet access. The class is written in HTML so any browser with a Flash (version 6 or higher) player will work
To do the lab students must have access to an SystemVerilog simulator.

COURSE OUTLINE: SV101 Class Content

Chapter 1 Introduction
Lab Key

Chapter 2 New Procedural Blocks
Lab1 – always_comb
Lab2 – always_ff
Lab3 – always_latch
Lab4 – always
Quiz – New Procedural Blocks

Chapter 3 Data Types
Lab5 – bit Data Type
Lab6 – logic Data Type
Lab7 – byte Data Type
Lab8 – Open
Lab9 – int Data Type
Lab10 – shortint Data Type
Lab11 – longint Data Type
Lab12 – integer Data Type Limits
Lab13 – Signed and Unsigned Integers
Lab14 – Four And Two State Simulations
Lab15 – Relaxation Of wire/reg Data Types
Lab16 – char Data Types
Lab17 – Initialization of Variables at Declaration1
Lab18 – User Defined Types
Lab19 – wire vs bit at initialization
Lab20A – Enumeration
Lab20B – Enumeration
Lab20C – Enumeration
Lab20D – Enumeration
Lab20E – Enumeration
Lab21 open
Lab22 – Enumeration Methods
Lab23 – FSMs and Enumeation
Lab24 – Initialization of Variables at Declaration
Quiz – Data Types

Chapter 4 Hierarchy
Lab25 – Compilation Unit
Lab26 – New Data Type Useage for Ports
Lab27 – Implicit . Name Connections
Lab28 – Implicit .* Name Connections
Lab29 – New Syntax for Ports
Lab30 – Ref Ports
Lab31 open
Quiz – Hierarchy

Chapter 5 Structures
Lab32 – Structures – Annonymous
Lab33 – User Typed Packed Structures
Lab34 open
Lab35 – Structures – Annonymous – Unpacked
Lab36 – Typed Structures – Packed
Lab37 – Structures – Using Default Values
Lab38 – Structures – Unpacked
Lab39 – Structures – Structures in Functions
Lab40 – Structures – Structures in Tasks
Quiz – Structures

Chapter 6 Unions
Lab41 -Unions – Dimensions
Lab42 – Union 32 Bits Types
Quiz – Unions

Chapter 7 Arrays
Lab43 -Unpacked Arrays
Lab44 – Unpacked Array Defaults
Lab45 -Packed Arrays
Lab46 – Arrays: System Function $bits
Lab47 – Arrays: System Function $dimensions
Lab48 – Arrays: System Function $high
Lab49 – Arrays: System Function $increment
Lab50 – Arrays: System Function $left
Lab51 – Arrays: System Function $right
Lab52 – Arrays: System Function $low
Lab53 open
Lab54 – Multi-Dimensional Packed Arrays
Lab55 – Packed Arrays as Ports
Lab56 – Array Initialization
Lab57 – Indexing and Slicing Arrays
Lab58A – Arrays Assigning (Packed Arrays)
Lab58B – Arrays Assigning (Unpacked Arrays)
Quiz – Arrays

Chapter 8 New SystemVerilog Operators
Lab59 – New Operator +=
Lab60 – New Operator -=
Lab61 – New Operator *=
Lab62 – New Operator /=
Lab63 – New Operator %=
Lab64 – New Operator &=
Lab65 – New Operator |=
Lab66 – New Operator ^=
Lab67 – New Operator “<<=”
Lab68 – New Operator “>>=”
Lab69 – New Operator <<<=
Lab70 – New Operator >>>=
Lab71- New Operator – Pre and Post Increment ++
Lab72 – New Operator – Pre and Post Decrement —
Lab73 – do/while
Lab74 open
Quiz – SystemVerilog Operators

Chapter 9 Functions in SystemVerilog
Lab76A – Function Return
Lab76B – Empty Functions
Lab77 – Named End Functions
Lab78 – Function – Formal Argument
Lab79 – Function – Passing Arguments by Name
Lab80 – Void Funtions
Lab81 – Default Direction on Funtion Inputs
Lab82 – Automatic Functions
Quiz – Functions

Chapter 10 Tasks in SystemVerilog
Lab83A – Task Return
Lab83B – Automatic Tasks
Lab84 – Tasks and Function and Optional begin/end
Lab85 – Named endtask
Lab86 – Passing Arguments By Name
Lab87 – Formal Arguments
Quiz – Tasks

Chapter 11 Interface
Lab88 – Interface- General Example
Lab89 – Interface- Modports
Lab90 open
Lab91 – Functions in an Interface
Lab92 – Tasks in an Interface
Lab93 open
Quiz – Interfaces

Chapter 12 case and if statements
Lab94 – case Statment: Case Unique
Lab95 – case Statment: Priority Case
Lab96 – if Statment: Unique If
Lab97 – if Statment: Priority If
Lab98 open
Lab99 open
Quiz – Case and Ifs
Miscelaneous Labs
Lab75 – for loop enhancements
Lab100 – Named Begin/End Block
Lab101 – Expanding of ‘1
Lab102 open
Lab103 open
Lab104 – Begin/End Variable Declaration
Lab105 – Break Statment
Lab106 – Continue Statement

Course Fee Schedule: Registration is On-Going
IEEE Members $300
Non-members $350