Recent progress in understanding the electrical reliability of GaN High-Electron Mobility Transistors

Reliability – 6:00 PM, Tuesday, 10 February

Recent progress in understanding the electrical reliability of GaN High-Electron Mobility Transistors

 GaN High-Electron Mobility Transistors (HEMTs) are well on their way to revolutionizing RF, microwave and millimeter-wave communications and radar systems. GaN FETs are also uniquely poised to have a disruptive impact in electrical power management. In all these applications, device reliability remains a significant concern.

 As the field has expanded, great progress has recently taken place in understanding GaN transistor degradation, especially under high-voltage stress. Detailed electrical studies coupled with comprehensive failure analysis involving a variety of techniques have revealed a rich picture of degradation. Early studies showed that high voltage degradation of GaN HEMTs was characterized by a critical voltage (V_crit) at which the device gate current abruptly increases. For stress voltage beyond V_crit, prominent degradation was observed in the drain current and other electrical parameters of the device. More recently, it has been shown that degradation in the gate current can occur for voltages below the critical voltage suggesting that stress time is a key variable in degradation. Cross-section TEM and planar imaging techniques have shown that high-voltage stress induces prominent structural defects such as grooves, pits and cracks in the GaN cap and AlGaN barrier at the edge of the gate. The evolution of these defects correlates well with that of electrical degradation. Recently, a similar pattern of degradation has been observed under high-power DC and RF stress, although not in a consistent way. A significant recent finding is the role that moisture plays in the formation of these structural defects. This suggests a path for mitigation. Separately from device degradation, a significant anomaly affecting GaN transistors is electron trapping which can severely upset device operation on a wide time domain. This talk will review recent research on the electrical reliability and trapping of GaN HEMTs.

Jesús A. del Alamo is the Director of the Microsystems Technology Laboratories at Massachusetts Institute of Technology. He obtained a Telecommunications Engineer degree from the Polytechnic University of Madrid in 1980 and MS and PhD degrees in Electrical Engineering from Stanford University in 1983 and 1985, respectively. From 1985 to 1988 he was with NTT LSI Laboratories in Atsugi (Japan) and since 1988 he has been with the Department of Electrical Engineering and Computer Science of Massachusetts Institute of Technology where he is the Donner Professor. His current research interests are centered on nanoelectronics based on compound semiconductors. He is also investigating online laboratories for science and engineering education.

Prof. del Alamo was an NSF Presidential Young Investigator. He is a member of the Royal Spanish Academy of Engineering and Fellow of the IEEE. He currently serves as Editor of IEEE Electron Device Letters. In 2012 he received the Intel Outstanding Researcher Award in Emerging Research Devices, the SRC Technical Excellence Award, and the IEEE EDS Education Award.

This meeting will be held on Tuesday, February 10, 2015 at MIT Lincoln Laboratory, Lexington, MA. It will begin with personal networking at 5:30 PM. The presentation will follow at 6:00 PM.  Refreshments, compliments of the Reliability Chapter, will be available.  You do not need to belong to IEEE to attend this event; however we welcome your consideration of IEEE memberships as career enhancing technical affiliations. We request that you register to attend by Friday, February 6, so we can plan the refreshments.

You can register on-line by visiting the Reliability Chapter website at http://www.ieee.org/bostonrel

MIT Lincoln Laboratory is located at 244 Wood Street, Lexington, MA 02421.

Directions to Lincoln Laboratory: (from Interstate-95 / Route 108)

From the north (southbound):

• Take Exit 31B and merge onto Routes 4/225 towards Bedford
• Stay in right lane and go 0.3 miles from exit.
• Use Right Turning Lane just before traffic light to access Hartwell Ave. at 1st Traffic Light.
• Follow Hartwell Ave. for about 1.2 miles to Wood St.
• Turn left onto Wood Street and drive 0.3 mile.
• Turn right into MIT Lincoln Laboratory at the Wood Street Gate
• Have a valid driver’s license to present to security:
• Attending the IEEE Reliability presentation in the cafeteria.

From the south (northbound)

• Take Exit 30B and merge onto Route 2A – Stay in right lane
• Go about 0.4 miles to second traffic light and turn right on to Mass. Ave (opposite Minuteman Tech.).
• Follow Mass. Ave for ~ 0.4 miles.
• Turn left onto Wood Street and drive for 1.0 mile.
• Turn left into MIT Lincoln Lab at the Wood Street Gate
• Have a valid driver’s license to present to security:
• Attending the IEEE Reliability presentation in the cafeteria.
• Park in the Visitor Parking area. To get to the Cafeteria, proceed toward the Main Entrance of MIT Lincoln Laboratory, but before entering the building, proceed down the stairs hidden to the left of the Main Entrance. Turn right at the bottom of the stairs and enter the building through the Cafeteria entrance. The Cafeteria is located directly ahead.

Web map link:  http://www.ll.mit.edu/about/map.html