Incidentals:

• Price: $105.
• Duration: 3 hours
• Instructor:  Greg Caswell

Abstract: In today’s fast-paced, highly competitive electronics market, producing reliable products is critical to a company’s success. Business case studies have consistently shown that performing comprehensive design reviews during product development is the only proven method for ensuring a reliable product.  Most companies have some type of design review process; but some fairly straightforward enhancements can drive substantial product improvements.  Verifying design robustness early in the process is both effective and efficient and can easily be incorporated into existing design review processes.  This presentation will cover how to use a new or existing Design Review Process to truly Design for Reliability and verify robust design.

A 5 step execution plan with tailoring to different markets will be discussed:

• Initial Reliability Assessment: Performed by Subject Matter Experts (SME)
• Limited 1st Order Physics of Failure (PoF) Based Simulation Based on SME Identification of Critical Components: Algorithms (Coffin-Manson, Steinberg, etc.) Identified in Industry Standards (IPC SM-785, VITA 51.2, JESD47)
• Comprehensive 1st Order PoF-Based Simulation: Automated Design Analysis
• Full 3D FEA & Thermal Simulation
• Test Plan Development & Execution

The 5 steps will incorporate Physics of Failure, electrical, mechanical, thermal, testing, and manufacturability topics.

Target audience:  Engineers involved in the design, manufacturing, assembly, testing and/or reliability of electronic packages, circuit board assemblies

Benefits of attending:

• Reliability Test plan development for electronic assemblies
• Methodology for simulating failure modes of electronic assemblies
• Three dimensional FEA

Instructor: Greg Caswell

Greg Caswell, a Lead Consulting Engineer for Ansys Corporation, is an industry recognized expert in the fields of SMT, advanced packaging, printed board fabrication, circuit card assembly, and bonding solutions using nanotechnology. He has been well-regarded as a leader in the electronics contract manufacturing and component packaging industries for the past 50 years. He has presented over 270 papers at conferences all over the world and has taught courses at IMAPS, SMTA and IPC events.  He helped design the 1st pick and place system used exclusively for SMT in 1978, edited and co-authored the 1st book on SMT in 1984 for ISHM and built the 1st SMT electronics launched into space.  Be on the lookout for his new book entitled Design for Excellence in Electronics Manufacturing due out in September 2020. Greg has won several awards including the IMAPS Lifetime Achievement Award in 2018, the ISHM Daniel C. Hughes Award (highest award given to an individual), ISHM Fellow of the Society Award and the Tracor Technical Innovation Award.

Incidentals:

• Price: $70
• Duration: 2 hours
• Instructor: Greg Caswell

Abstract: Since the advent of surface mount technology back in the 1970’s we, as an industry, have continually worked to miniaturize our products.  This evolution of product design has impacted us at the semiconductor, package, circuit board and system levels.  So, the question is, Why do Electronics Fail Under Thermal Cycling and What Can We Do About it During the Design Cycle?

At the package level issues with bond wires and stacked die add to the reliability impact.  At the printed circuit board level issues with solder wearout, solder phase coarsening, PWB laminates and glass materials, plated through hole (PTH) fatigue, and the impact of potting can also affect reliability.

What drives these issues is that we use a variety of materials e.g. semiconductors, ceramics, metals and polymers.  We then bond them together with other materials like solder and adhesives.  Each of these materials has a Coefficient of Thermal Expansion (CTE) that is unique and therefore expands and contracts at different rates.

Being able to model the assembly with respect to Reliability Physics is an effective way to identify the issues in a design even prior to creating a prototype.  This talk will delineate some of the issues involved in device and PWB packaging as well as how a modeling approach can facilitate their identification so they can be corrected.

Target audience:  Engineers involved in the design, manufacturing and/or reliability of complex printed circuit board assemblies.

Benefits of attending

• Learn about different failure modes with each level of electronic packaging/assembly
• Mitigation methods for the relevant failure modes

Instructor: Greg Caswell

Greg Caswell, a Lead Consulting Engineer for Ansys Corporation, is an industry recognized expert in the fields of SMT, advanced packaging, printed board fabrication, circuit card assembly, and bonding solutions using nanotechnology. He has been well-regarded as a leader in the electronics contract manufacturing and component packaging industries for the past 50 years. He has presented over 270 papers at conferences all over the world and has taught courses at IMAPS, SMTA and IPC events.  He helped design the 1st pick and place system used exclusively for SMT in 1978, edited and co-authored the 1st book on SMT in 1984 for ISHM and built the 1st SMT electronics launched into space.  Be on the lookout for his new book entitled Design for Excellence in Electronics Manufacturing due out in September 2020. Greg has won several awards including the IMAPS Lifetime Achievement Award in 2018, the ISHM Daniel C. Hughes Award (highest award given to an individual), ISHM Fellow of the Society Award and the Tracor Technical Innovation Award.

Incidentals:

• Price: $105.
• Duration: 3 hours
• Instructor: Greg Caswell

Abstract: Solder provides the structural and electrical connection between a printed wiring board (PWB) and electrical components.  Solder is the most common material used for assembling electronics. However, while most materials only experience elastic deformation during use, solder is also one of the few structural materials that is expected to also undergo significant inelastic deformation during its lifetime.

Both elastic and inelastic deformation damages solder, causing the solder joints to fail, and consequentially the printed circuit assembly to fail. Predicting when the solder joint fails is critical when using solder in harsh use environments.  These harsh environments have loads that can come in several forms (i.e., drop/shock, vibration, temperature cycling).

While vibration causes high cycle fatigue of solder, most solder fatigue failures in electronics are thermo-mechanically driven due to temperature cycling which causes significant deformations and stresses due to coefficient of thermal expansion (CTE) mismatches between the PWB and components. To predict solder failure, a damage model must be used that relates deformation of the solder to cycles to printed circuit board assembly failure.

In this tutorial, we will discuss material characterization of various solder alloys, predictive solder fatigue damage models using a physics-of-failure approach (PoF) for printed circuit board assemblies and how to develop damage models using simulation and testing.

Target audience:  Engineers involved in the design, simulation and modeling, manufacturing and/or reliability of complex printed circuit board assemblies.

Benefits of attending:

• Learn about different solder alloys and their failure mechanisms
• Characterizing solder material properties for simulation and modeling
• Methods for predicting reliability of electronic assemblies

Greg Caswell, a Lead Consulting Engineer for Ansys Corporation, is an industry recognized expert in the fields of SMT, advanced packaging, printed board fabrication, circuit card assembly, and bonding solutions using nanotechnology. He has been well-regarded as a leader in the electronics contract manufacturing and component packaging industries for the past 50 years. He has presented over 270 papers at conferences all over the world and has taught courses at IMAPS, SMTA and IPC events.  He helped design the 1st pick and place system used exclusively for SMT in 1978, edited and co-authored the 1st book on SMT in 1984 for ISHM and built the 1st SMT electronics launched into space.  Be on the lookout for his new book entitled Design for Excellence in Electronics Manufacturing due out in September 2020. Greg has won several awards including the IMAPS Lifetime Achievement Award in 2018, the ISHM Daniel C. Hughes Award (highest award given to an individual), ISHM Fellow of the Society Award and the Tracor Technical Innovation Award.