Incidentals:

• Price: $70
• Duration: 2 hours
• Instructor: Greg Caswell

Abstract: Since the advent of surface mount technology back in the 1970’s we, as an industry, have continually worked to miniaturize our products.  This evolution of product design has impacted us at the semiconductor, package, circuit board and system levels.  So, the question is, Why do Electronics Fail Under Thermal Cycling and What Can We Do About it During the Design Cycle?

At the package level issues with bond wires and stacked die add to the reliability impact.  At the printed circuit board level issues with solder wearout, solder phase coarsening, PWB laminates and glass materials, plated through hole (PTH) fatigue, and the impact of potting can also affect reliability.

What drives these issues is that we use a variety of materials e.g. semiconductors, ceramics, metals and polymers.  We then bond them together with other materials like solder and adhesives.  Each of these materials has a Coefficient of Thermal Expansion (CTE) that is unique and therefore expands and contracts at different rates.

Being able to model the assembly with respect to Reliability Physics is an effective way to identify the issues in a design even prior to creating a prototype.  This talk will delineate some of the issues involved in device and PWB packaging as well as how a modeling approach can facilitate their identification so they can be corrected.

Target audience:  Engineers involved in the design, manufacturing and/or reliability of complex printed circuit board assemblies.

Benefits of attending

• Learn about different failure modes with each level of electronic packaging/assembly
• Mitigation methods for the relevant failure modes

Instructor: Greg Caswell, a Lead Consulting Engineer for Ansys Corporation, is an industry recognized expert in the fields of SMT, advanced packaging, printed board fabrication, circuit card assembly, and bonding solutions using nanotechnology. He has been well-regarded as a leader in the electronics contract manufacturing and component packaging industries for the past 50 years. He has presented over 270 papers at conferences all over the world and has taught courses at IMAPS, SMTA and IPC events.  He helped design the 1st pick and place system used exclusively for SMT in 1978, edited and co-authored the 1st book on SMT in 1984 for ISHM and built the 1st SMT electronics launched into space.  Be on the lookout for his new book entitled Design for Excellence in Electronics Manufacturing due out in September 2020. Greg has won several awards including the IMAPS Lifetime Achievement Award in 2018, the ISHM Daniel C. Hughes Award (highest award given to an individual), ISHM Fellow of the Society Award and the Tracor Technical Innovation Award.

Incidentals:

Abstract: In recent decades as the industry has moved away from vertical integration to a geographically diffuse and disconnected electronic supply chain, maintaining quality control over supplier practices has been challenging. Cost constraints have resulted in the use of Commercial Off the Shelf (COTS) electronic components in several high reliability industry verticals such as aerospace, medical and defense for many years now. Navigating the supply chain in trying to meet high reliability standards has been challenging.

In this tutorial, several case studies will serve as examples to demonstrate what can go wrong in using off the shelf components. Risk assessments and management practices that companies can use to mitigate and control the technical, business and supply chain risks associated with COTS components in the electronic supply chain, will be discussed. Sourcing, qualification, product support, and roadmap lifecycle decisions the component suppliers make, will be discussed.

Target audience: Engineers/managers involved in the design, manufacturing and/or reliability of electronic products/systems, and printed circuit board assemblies.

Benefits of attending:

• How to avoid common mistakes in use of COTS components
• Mitigation methods for the relevant failure modes in the use of COTS components
• Keywords/Hashtags: Electronic reliability, MLCC, failure modes and mechanisms

Instructor: Dock Brown, CRE

Dock Brown brings his more than 30 years of electronics reliability experience to clients of Ansys. Prior to joining Ansys, he spent 20 years at Medtronic where he most recently concentrated on cross business unit implementation of reliability initiatives for Class III medical devices. He was also responsible for supplier assessment and approval, on-going supplier audits, failure analysis, corrective actions, MRB, sampling, and ultimately full accountability for quality and reliability of COTS and custom parts and assemblies from a worldwide supplier base. Earlier in his career, Mr. Brown also spent time at Sundstrand Data Control where he led the implementation of the Boeing AQS program and with Olin Aerospace.

As a volunteer, he has been involved with ASQ, IEEE, IPC, and SMTA. He was the keynote speaker at the SMTA Cleaning Conference. He has taught design for reliability, tin whiskers, statistics, design of experiments, and contributed to standards development. He has won the SMTA Distinguished Speaker award and the SMTA Microelectronics Conference Best Paper award.

Incidentals:

• Price: $105.
• Duration: 3 hours
• Instructor: Greg Caswell

Abstract: Electrostatic Discharge (ESD) has been an issue in the electronics industry for years.  As gate geometries continue to get smaller and smaller the potential for ESD failures increases.  Similarly, the newest packaging technologies also make it easier to mishandle the components.  In some cases the failures are latent and don’t manifest themselves for a period of time making failure analysis and root cause assessments more difficult.

This course will address ESD Physics, a Classification System for Electronic Devices, ESD Protection Methods and Testing approaches.

ESD can be defined as a single-event, rapid transfer of electrostatic charge between two objects, usually resulting when two objects at different potentials come into direct contact with each other.  ESD can also occur when a high electrostatic field develops between two objects in close proximity. Also defined as an over-voltage event with a duration of 1 nanosecond to 1 microsecond that is primarily an issue during non-operational manufacturing and handling.

Topics addressed for the student will include:

• ESD Models (CDM, HBM, MM, CBM)
• Triboelectric Properties and Materials
• The Industry Challenge
• ESD Prevention (IC Level, Package Level, and System Level) and Specifications
• Design Practices for ESD Management
• ESD Scanning and Susceptibility Analysis Techniques
• The Role of Capacitance
• Diode and TVS Protection Schemes
• PESD Devices
• ESD Prevention in Manufacturing
  • Sources of ESD
  • Prevention Tools and Equipment
  • Packaging and Humidity Effects
• Failure Analysis Techniques
• Distinguishing Between ESD and EOS

Target audience:  Engineers involved in the design, manufacturing, assembly, testing and/or reliability of electronic packages, circuit board assemblies

Benefits of attending:

• ESD Models (CDM, HBM, MM, CBM)
• ESD Prevention (IC Level, Package Level, and System Level) and Specifications
• Design Practices for ESD Management
• Failure Analysis Techniques
• Distinguishing Between ESD and EOS

Instructor: Greg Caswell, a Lead Consulting Engineer for Ansys Corporation, is an industry recognized expert in the fields of SMT, advanced packaging, printed board fabrication, circuit card assembly, and bonding solutions using nanotechnology. He has been well-regarded as a leader in the electronics contract manufacturing and component packaging industries for the past 50 years. He has presented over 270 papers at conferences all over the world and has taught courses at IMAPS, SMTA and IPC events.  He helped design the 1st pick and place system used exclusively for SMT in 1978, edited and co-authored the 1st book on SMT in 1984 for ISHM and built the 1st SMT electronics launched into space.  Be on the lookout for his new book entitled Design for Excellence in Electronics Manufacturing due out in September 2020. Greg has won several awards including the IMAPS Lifetime Achievement Award in 2018, the ISHM Daniel C. Hughes Award (highest award given to an individual), ISHM Fellow of the Society Award and the Tracor Technical Innovation Award.

Incidentals:

Abstract: The multilayer ceramic capacitor (MLCC) has become a widely used electronics component. The MLCC technologies have gone through several material and process changes such as the shift from precious metal electrode (PME) configurations which were predominantly silver/palladium to base metal electrodes (BME) dominated by nickel. The MLCC industry is now in the midst of an unprecedented set of challenges similar to the Moore’s Law challenges being faced by the semiconductor industry. Critical changes have included decreasing voltages and increasing layer count resulted in both quality and reliability problems. This has resulted in failure modes such as dielectric breakdown and oxygen vacancy migration. This tutorial will discuss common failures, root cause, and mitigation methods involving supplier selection and qualification.

Target audience: Engineers/managers involved in the design, manufacturing and/or reliability of electronic products/systems, and printed circuit board assemblies.

Benefits of Attending:

• How to avoid common mistakes in the use of MLCCs
• Mitigation methods for the relevant MLCC failure modes
• Keywords/Hashtags: Electronic reliability, Multilayer ceramic chip capacitor (MLCC), failure modes and mechanisms

Instructor:  Dock Brown, CRE

Dock Brown brings his more than 30 years of electronics reliability experience to clients of Ansys. Prior to joining Ansys, he spent 20 years at Medtronic where he most recently concentrated on cross business unit implementation of reliability initiatives for Class III medical devices. He was also responsible for supplier assessment and approval, on-going supplier audits, failure analysis, corrective actions, MRB, sampling, and ultimately full accountability for quality and reliability of COTS and custom parts and assemblies from a worldwide supplier base. Earlier in his career, Mr. Brown also spent time at Sundstrand Data Control where he led the implementation of the Boeing AQS program and with Olin Aerospace.

As a volunteer, he has been involved with ASQ, IEEE, IPC, and SMTA. He was the keynote speaker at the SMTA Cleaning Conference. He has taught design for reliability, tin whiskers, statistics, design of experiments, and contributed to standards development. He has won the SMTA Distinguished Speaker award and the SMTA Microelectronics Conference Best Paper award.

Incidentals:

• Price: $70.
• Duration: 2 hours
• Instructor:  Doc Brown, CRE

Abstract: The semiconductor industry has witnessed steady growth over the last few years thanks to emerging applications, which are driving the growth of major semiconductor components. Reliable operation of these components is very important in any given application and in order to ensure reliability component parts must receive extensive testing and burn-in. Despite this, integrated circuit (IC) failures are still inevitable.

One of the common failure mechanisms that affects all IC components irrespective of the type of application is electrical overstress (EOS). EOS can affect components without warning, and when EOS does happen, the damage is done, and the functionality cannot be recovered. This often results in significant impact to consumers of ICs in the entire supply chain, raising concerns about the root cause of failure, reliability of other fielded components and increased costs.

In this webinar, we will discuss the possible root causes of EOS failures, why it ranks high in the failure pareto, and ways to mitigate EOS failure risks.

Target audience: Engineers involved in the design, manufacturing and/or reliability of complex printed circuit board assemblies.

Benefits of attending:

• Learn about the impact of Electrical Overstress (EOS) on semiconductor devices
• Learn about the Impact of Absolute Maximum Rating (AMR) on EOS failures
• Root Causes of EOS failure mechanisms
• Mitigation methods for the relevant failure modes
  Keywords/Hashtags: Electrical Overstress (EOS), Electrostatic discharge (ESD), Electronics reliability, failure modes and mechanisms, transient Absolute Maximum Rating (tAMR)

Instructor:  Ashok Alagappan

Ashok Alagappan has 15 years of experience in the Semiconductor industry, specializing in design and manufacturing of semiconductor products. He has managed products through their life cycle, from introduction in the Fab to qualification. At Ansys, he is working with customers across the spectrum, from aerospace, automotive to commercial, providing expert analysis and recommendations for defining and improving reliability of electronic products and IC components. He has developed an IC wear out tool to predict the lifetime characteristics of Integrated Circuit components in high reliability applications like aerospace, defense, automotive, among others. He has built models to characterize the intrinsic wear out failure mechanisms of ICs and has implemented the tool in the Ansys Sherlock ADA™ software product.

Incidentals:

Abstract: Performance enhancements and feature shrinkage in electronics have enabled explosive growth in the areas of Internet of Things (IOT) grow and wearable electronics. Connectors provide the critical function of communication between devices and as well as providing. As critical as they are, separable connectors are often the first item to fail in electronics. This problem is worse for electronics in challenging environments like automotive, as well as increased regulatory requirements in certain industries like medical and industrial. Therefore, the risk of connector failures increases in these applications. This tutorial will discuss connector failures, details of contact physics, contact plating options, normal force requirements and general tradeoffs that frequently occur when designing or selecting a connector for an application. Design guidance on how to prevent connector failures will be provided in this tutorial.

Target audience: Engineers/managers involved in the design, manufacturing and/or reliability of electronic products/systems, and printed circuit board assemblies.

Benefits of attending:

• How to avoid common mistakes in connector design and applications
• Mitigation methods for the relevant failure modes for connectors
• Keywords/Hashtags: Electronic reliability, Connectors, Connector failure modes and mechanisms, electronic component failures

Instructor: Dock Brown, CRE

Dock Brown brings his more than 30 years of electronics reliability experience to clients of Ansys. Prior to joining Ansys, he spent 20 years at Medtronic where he most recently concentrated on cross business unit implementation of reliability initiatives for Class III medical devices. He was also responsible for supplier assessment and approval, on-going supplier audits, failure analysis, corrective actions, MRB, sampling, and ultimately full accountability for quality and reliability of COTS and custom parts and assemblies from a worldwide supplier base. Earlier in his career, Mr. Brown also spent time at Sundstrand Data Control where he led the implementation of the Boeing AQS program and with Olin Aerospace.

As a volunteer, he has been involved with ASQ, IEEE, IPC, and SMTA. He was the keynote speaker at the SMTA Cleaning Conference. He has taught design for reliability, tin whiskers, statistics, design of experiments, and contributed to standards development. He has won the SMTA Distinguished Speaker award and the SMTA Microelectronics Conference Best Paper Award.