Modern Applications of RISC-V CPU Design Course

September 1, 2021 – September 30, 2021 all-day America/New York Timezone
Self-Paced, On Demand Course

Speaker: Steve Hoover, Redwood, EDA

Type of Course: Self-paced, on demand Course. Lab format

Dates:  9/1/2021 – 9/30/2021

Registration Deadline:  Decision date to run/cancel this course:  August 25, 2021

Register by Wednesday, August 25, 2021 for the early registration rate. 

Members:  $275.00  – Non-Members: $320 

After August 25, 2021: 

Members:  $350.0 – Non Members: $395


Course Overview:  CPUs are a fundamental building block of complex SoCs, and RISC-V is taking hold as the ISA of choice. In this workshop, you will create a Verilog RISC-V CPU from scratch, and you will modify this CPU to be suitable for different applications. You will learn and use modern techniques, using Transaction-Level Verilog to generate and modify your Verilog code more reliably, in far less time. You will discover how concepts like pipelining and hazards can be incorporated easily using timing-abstract design principles. All labs will be completed online in the IDE for open-source circuit design. The skills you learn will be applicable far beyond CPU design.

Outline of Topics to be Covered:  Digital logic using TL-Verilog and Makerchip – combinational logic – sequential logic – pipelined logic – validity – a calculator circuit Basic RISC-V CPU microarchitecture – single-cycle CPU microarchitecture – testbench, test program, and lab setup for your CPU – fetch, decode, and execute logic for RISC-V subset – control flow logic Pipelined RISC-V subset CPU microarchitecture – simple pipelining of the CPU – hazards and PC redirects Completing the RISC-V CPU – data memory and load/store – remaining RISC-V (RV32I) instructions

Course Format: – self paced, on demand course, providing attendees a flexible schedule – access to content for 30 days – pre-scheduled live Zoom and chat sessions with instructors during the 30 day access period – offline chat available with instructors during the entire 30 day access period (reply within 24 hours).

Target Audience: Engineers interested in a career in digital logic design or adjacent disciplines, including experienced engineers looking to modernize their skill set. Prerequisites: An engineering education and basic understanding of digital logic. (Verilog knowledge is not a prerequisite.)

Benefits of Attending: – Develop a solidified understanding of pipelined CPU design through hands-on labs. – Acquire knowledge of advanced digital circuit design methodology. – Gain exposure to an open-source design ecosystem. Speaker Bio: Steve Hoover is the founder of Redwood EDA, an early-stage startup focused on advanced silicon design methodology and tools. Steve is a former logic design lead for DEC, Compaq, and Intel and has extensive experience designing high-performance server CPUs and network switches.

Social Media Profile: System Requirements: All resources are free and online; no download or installation required.

We will use Slack, Zoom, GitHub Classroom, and

Registration click here: