Fall 2016 Course
Dates: Tuesdays, Sept. 27, Oct. 4, 11, 18, 25
Time: 6 – 8 pm
Decision date: Tuesday, September, 20, 2016
Early Registration Date deadline: September 15
Before Early Registration Date:
IEEE Members $150
Non-members $180
After Early Registration Date:
IEEE Members $180
Non-members $195
WHERE: MIT Lincoln Laboratory, Cafeteria
3 Forbes Rd,
Lexington, MA 02421
Light snacks will be provided
Phone 781-245-5405
email sec.boston@ieee.org
Fax 781-245-5406
If paying by check, the check must be received before the appropriate dates for Early Registration and Decision Dates.
Make Checks payable and send to:
IEEE Boston Section
One Centre Street, Suite 203
Wakefield, MA 01880
Overview
Modern Topics in Power Amplifiers (MTT Chapter Course)
This five week lecture series is intended to give a tutorial overview of the latest developments in power amplifier technology. It begins with a review of RF power amplifier concepts then teaches the modern MMIC design flow process. Efficiency and linearization techniques are discussed in the following weeks. The course is concluded with a hands on demonstration and exercise, brought to you by National Instruments, where participants will see how DPD and envelope tracking are implemented with actual hardware.,
Who Should Attend
The material is taught at a level that any electrical engineer should be able to understand. If your memory of RF amplifier concepts is a little rusty, make sure to catch the first lecture on September 27th.
Course Goals
This course aims to give a broad overview of state-of-the-art PA techniques with practical hardware demonstrations.
Schedule
September 27th
Amplifier Basics, by Dr. Nestor Lopez of MIT Lincoln Laboratory
- RF Amplifier Characteristics
- Linearity
- Efficiency
- Modes of Operation
- LNA vs. HPA
- Amplifier Classes
- Amplifier Implementation
- Small Signal Theory
- Large-Signal Transistor Characterization
- Bias Networks
- Power Combining
October 4th
MMIC Design Flow, by Dr. Youngho Suh of MIT Lincoln Laboratory
- Foundry selection with PDK availability
- Frontend Design
- Bias selection with loadline / loadpull, reliablility
- Drive budget estimation for multi-stage cascade design
- Periphery estimation for target specification
- Matching topology selection
- Circuit Simulation
- Small signal linear simulation
- Large signal linear simulation (Cripps method)
- Large signal nonlinear simulation
- Layout and EM simulation
- Real estate war!
- Package interface
- 2 and 3D EM simulation tools
- Verification
- DRC and LVS
- Sensitivity, yields, stability…etc
October 11th
High Efficiency Architectures, by Dr. Andrew Zai of MIT Lincoln Laboratory
- Fundamental Equations of Linearity and Efficiency
- Classes of Amplifiers and their Theoretical Efficiencies
- Class A, AB, B, C
- Compression and Switched Mode PAs
- Compression
- Class D, Class F/F^-1
- High Efficiency Architectures
- Outphasing
- Doherty
- Envelope Tracking
Digital Transmitter, Dr. Rui Ma of Mitsubishi Electric Research Labs
- Class-S mode
- GaN for Digital TX
- Power encoding
- Delta-sigma Modulation
- Pulse Width Modulation
- Implementation of Digital TX
- FPGA
- ASIC
October 18th
Predistortion Techniques, by Dr. Andrew Bolstad of MIT Lincoln Laboratory
- Why nonlinear systems?
- Linear vs. Nonlinear Systems
- Predistortion and Equalization
- Nonlinear System Models
- AM/AM and AM/PM
- Box Models
- Memory Polynomials and Generalized Memory Polynomials
- Volterra Kernels
- Pruned / Sparse Volterra Kernels
- Identification of Model Parameters
- Direct / Indirect Learning
- Training signals
Digital Predistortion System and Demo, by Dr. Kevin Chuang of NanoSemi, Inc.
- DPD System Architecture and Consideration
- Real-Time DPD Demonstration
- Traditional Linearization based on Static DPD and Generalized Memory Polynomials
- NanoSemi’s Ultra-Wideband Proprietary Linearization
- Benefits of NanoSemi’s Linearizer
October 25th
Presentation and Hands on Hardware Demonstration from National Instruments on Digital Predistortion and Envelope Tracking
ET/DPD Measurement System Introduction
- Instrumentation requirements for testing ET/DPD-enabled PA’s
- [Hands-on] PA measurement walk-through (EVM, ACLR/SEM, AM-AM/AM-PM)
- [Demo] Effects of synchronization misalignment
- [Hands-on] ET shaping function
- [Hands-on] DPD model identification
FPGA-based DPD reference design
- Motivation
- DPD potentially becoming a part of component test
- Prototyping algorithms
- Software-based DPD algorithm considerations
- Stimulus/response time, phase, amplitude alignment
- Model extraction
- Overview of system platform
- Vector Signal Transceiver (VST) architecture
- A look at the instrument’s DSP chain
- FPGA Algorithm
- Predistorter implementation
- Demo
- Efficient time/phase/amplitude alignment algorithm
- Demo
Linearize your own PA
- Attendee brings their own non-linear PA to test with measurement hardware