Low Power Design Essentials (THIS COURSE HAS BEEN POSTPONED)

When:
January 13, 2015 @ 6:00 pm – 7:00 pm America/New York Timezone
2015-01-13T18:00:00-05:00
2015-01-13T19:00:00-05:00
Where:
Crowne Plaza Hotel
15 Middlesex Canal Park Drive
Woburn, MA 01801
USA
Cost:
See below
Low Power Design Essentials             (THIS COURSE HAS BEEN POSTPONED) @ Crowne Plaza Hotel | Woburn | Massachusetts | United States

POSTPONED

 

 

 

 

 

 

THIS COURSE HAS BEEN POSTPONED. LOOK FOR FUTURE ANNOUNCEMENTS

Speaker:

Jerry Frenkil, VP of Engineering, NanoWatt Design, Inc.

Payment received by Dec. 29

IEEE Members $250
Non-members $275

Payment received after Dec. 29

IEEE Members $270
Non-members $290

Decision (Run/Cancel) Date for this Courses is :  Monday, January 5, 2015

Course Description

Power consumption has become a limiting factor in product design. For wireless devices, power consumption limits functionality due to battery life issues. For tethered devices, power consumption limits functionality due to constraints on heat generation and power availability. This short course will survey the wide variety of Low Power Design issues, techniques, and methodologies that have been developed in response to these challenges. It will provide electronics professionals a clear understanding of the design approaches and tradeoffs involved in developing power efficient devices and systems, covering a broad range of approaches from transistors to system architectures.

Outline

Session 1: Introduction and Circuit Level Power Optimizations
Motivations and Trends
Power and Energy Basics
Design Time, Runtime, and Standby techniques
Circuit level power optimization
Interconnect and clock power optimization

Session 2: Logic and System Level Power Optimizations
Arch, Algorithm, & system level power optimization
Memory power optimization
Circuits & Systems for Standby Power Optimization
Circuits & Systems for Runtime Power Optimization

Session 3: Design Methodologies and Advanced Topics
Ultra Low Power / Voltage Design
Low Power Design Methodologies
Power Integrity Methodologies
Summary and Perspective

Target Audience

System and ASIC developers, applications engineers, and design managers needing to understand how to estimate, analyze, and optimize power consumption

Benefits of attending Gain a broad, fundamental understanding of power consumption and how to manage and optimize it during different design phases and in different modes of system operation

Biography

Jerry Frenkil is VP of Engineering at NanoWatt Design, Inc. He has over 25 years experience in the electronics industry, including positions at Mostek, Prime Computer, VLSI Technology, Sente, and Sequence Design, where he was CTO and VP of R&D. Jerry has multiple patents and publications, including chapters in four books. Jerry has a BS in Electrical Engineering from the University of Texas.

Material with course

Slides will be distributed. Course will be based upon the text “Low Power Design Essentials”, by Jan Rabaey. (Instructor co-authored one of the chapters in the text.)