Electronic Reliability Tutorial Series

Electronic Reliability Tutorial Series

  • 7 Days: November 2, 3, 9, 10, 16, 17, and 18

Electronics perform critical functions in every major industry vertical, whether in automotive, aerospace, consumer, medical or industrial segments.  With the advent of newer technologies (both at the component and material levels), shrinkage of feature sizes, more stringent environments and sophisticated power requirements, electronics face increasing reliability risks.  The cost of reliability assurance activities is often a fraction of the cost of failure, with compounding benefits from conducting these activities early in the design process.

This set of five tutorials is aimed at organizations in every industry vertical, who would like to mitigate electronic failures.

Learn how to mitigate electronic reliability risks and prevent failures from industry renowned and award-winning experts.

Benefits of attending the series:

  • Understand common failure mechanisms at the electronic component/ package level and the printed circuit board assembly level
  • Learn about actionable mitigation methods for relevant failure modes/mechanisms
  • How to conduct reliability assessment for electronics
  • How to conduct a five-step design activity assurance for electronics
  • Electrostatic Discharge (ESD) failures and how to mitigate them
  • The Importance of Printed Circuit Board Cleanliness: How to Prevent No Fault Found Failures

Cost:

2 hour sessions
IEEE Members: $80
Non-members: $100

3 hour sessions
IEEE Members: $120
Non-members: $150

Series Tutorial Descriptions

  • Price: IEEE Members: $80; Non-members: $100
  • Pre-reqs: None
  • Continuing Ed Credits: $5 extra/course
  • When: November 2nd, 11:00AM – 1:00PM (EDT)
  • Duration: 1 day, 2 hours
  • Instructor: Greg Caswell

Abstract: Since the advent of surface mount technology back in the 1970’s we, as an industry, have continually worked to miniaturize our products.  This evolution of product design has impacted us at the semiconductor, package, circuit board and system levels.  So, the question is, Why do Electronics Fail Under Thermal Cycling and What Can We Do About it During the Design Cycle?

At the package level issues with bond wires and stacked die add to the reliability impact.  At the printed circuit board level issues with solder wearout, solder phase coarsening, PWB laminates and glass materials, plated through hole (PTH) fatigue, and the impact of potting can also affect reliability.

What drives these issues is that we use a variety of materials e.g. semiconductors, ceramics, metals and polymers.  We then bond them together with other materials like solder and adhesives.  Each of these materials has a Coefficient of Thermal Expansion (CTE) that is unique and therefore expands and contracts at different rates.

Being able to model the assembly with respect to Reliability Physics is an effective way to identify the issues in a design even prior to creating a prototype.  This talk will delineate some of the issues involved in device and PWB packaging as well as how a modeling approach can facilitate their identification so they can be corrected.

Target audience:  Engineers involved in the design, manufacturing and/or reliability of complex printed circuit board assemblies.

Benefits of attending

  • Learn about different failure modes with each level of electronic packaging/assembly
  • Mitigation methods for the relevant failure modes

Bio: Greg Caswell, a Lead Consulting Engineer for Ansys Corporation, is an industry recognized expert in the fields of SMT, advanced packaging, printed board fabrication, circuit card assembly, and bonding solutions using nanotechnology. He has been well-regarded as a leader in the electronics contract manufacturing and component packaging industries for the past 50 years. He has presented over 270 papers at conferences all over the world and has taught courses at IMAPS, SMTA and IPC events.  He helped design the 1st pick and place system used exclusively for SMT in 1978, edited and co-authored the 1st book on SMT in 1984 for ISHM and built the 1st SMT electronics launched into space.  Be on the lookout for his new book entitled Design for Excellence in Electronics Manufacturing due out in September 2020. Greg has won several awards including the IMAPS Lifetime Achievement Award in 2018, the ISHM Daniel C. Hughes Award (highest award given to an individual), ISHM Fellow of the Society Award and the Tracor Technical Innovation Award.

  • Price: IEEE Members: $80; Non-members: $100
  • Prereqs: None
  • When: November 3rd, 11:00AM – 1:00PM (EDT)
  • Duration: 1 day, 2 hours
  • Instructor: Greg Caswell  

Abstract: Reliability is the measure of a product’s ability to perform its specified function at the customer’s facility, in their use environment, over the desired lifetime.  Designing for reliability is the method for ensuring the reliability of a product or system during the design stage, before a physical prototype is produced is paramount.

This course will describe the failure modes associated with die attach, wire bonding, and solder joints using a Physics of Failure approach.  Strain energy equations will be discussed for the potential failure modes to help the student facilitate prediction of failure.

The course will then discuss the relatively new failure mechanism, that of silicon wearout.  As gate geometries have continued to shrink, the susceptibility of the device to fail has increased, to a point where some of the newer 14 nm feature devices will not hold up well in high reliability applications.  We will look at the intrinsic mechanisms of ICs to understand their susceptibility based on environments.

Finally, the course will introduce a method for assessing the microvias in a package to identify the highest stressor points and provide an approach for obviation.  Lastly, a short presentation on Electrostatic Discharge (ESD) and how to mitigate it will be presented.

Target audience:  Engineers involved in the design, manufacturing and/or reliability of electronic packages

Benefits of attending

  • Learn about different failure modes with each level of electronic packaging
  • Silicon wearout and microvia issues
  • ESD impact and mitigation

Bio: Greg Caswell, a Lead Consulting Engineer for Ansys Corporation, is an industry recognized expert in the fields of SMT, advanced packaging, printed board fabrication, circuit card assembly, and bonding solutions using nanotechnology. He has been well-regarded as a leader in the electronics contract manufacturing and component packaging industries for the past 50 years. He has presented over 270 papers at conferences all over the world and has taught courses at IMAPS, SMTA and IPC events.  He helped design the 1st pick and place system used exclusively for SMT in 1978, edited and co-authored the 1st book on SMT in 1984 for ISHM and built the 1st SMT electronics launched into space.  Be on the lookout for his new book entitled Design for Excellence in Electronics Manufacturing due out in September 2020. Greg has won several awards including the IMAPS Lifetime Achievement Award in 2018, the ISHM Daniel C. Hughes Award (highest award given to an individual), ISHM Fellow of the Society Award and the Tracor Technical Innovation Award.

  • Price: IEEE Members: $120; Non-members: $150
  • Pre-reqs: None
  • When: November 9th and 10th, 11:00AM – 12:30PM (EDT)
  • Duration: 2 days, 1.5 hours each day
  • Instructor: Greg Caswell

Abstract: In today’s fast-paced, highly competitive electronics market, producing reliable products is critical to a company’s success. Business case studies have consistently shown that performing comprehensive design reviews during product development is the only proven method for ensuring a reliable product.

Most companies have some type of design review process; but, some fairly straightforward enhancements can drive substantial product improvements.

Verifying design robustness early in the process is both effective and efficient and can easily be incorporated into existing design review processes.

This presentation will cover how to use a new or existing Design Review Process to truly Design for Reliability and verify robust design.

A 5 step execution plan with tailoring to different markets will be discussed:

  • Initial Reliability Assessment: Performed by Subject Matter Experts (SME)
  • Limited 1st Order Physics of Failure (PoF) Based Simulation Based on SME Identification of Critical Components: Algorithms (Coffin-Manson, Steinberg, etc.) Identified in Industry Standards (IPC SM-785, VITA 51.2, JESD47)
  • Comprehensive 1st Order PoF-Based Simulation: Automated Design Analysis
  • Full 3D FEA & Thermal Simulation
  • Test Plan Development & Execution

The 5 steps will incorporate Physics of Failure, electrical, mechanical, thermal, testing, and manufacturability topics.

Target audience:  Engineers involved in the design, manufacturing, assembly, testing and/or reliability of electronic packages, circuit board assemblies

Benefits of attending

  • Reliability Test plan development for electronic assemblies
  • Methodology for simulating failure modes of electronic assemblies
  • Three dimensional FEA

Bio: Greg Caswell, a Lead Consulting Engineer for Ansys Corporation, is an industry recognized expert in the fields of SMT, advanced packaging, printed board fabrication, circuit card assembly, and bonding solutions using nanotechnology. He has been well-regarded as a leader in the electronics contract manufacturing and component packaging industries for the past 50 years. He has presented over 270 papers at conferences all over the world and has taught courses at IMAPS, SMTA and IPC events.  He helped design the 1st pick and place system used exclusively for SMT in 1978, edited and co-authored the 1st book on SMT in 1984 for ISHM and built the 1st SMT electronics launched into space.  Be on the lookout for his new book entitled Design for Excellence in Electronics Manufacturing due out in September 2020. Greg has won several awards including the IMAPS Lifetime Achievement Award in 2018, the ISHM Daniel C. Hughes Award (highest award given to an individual), ISHM Fellow of the Society Award and the Tracor Technical Innovation Award.

  • Price: IEEE Members: $120; Non-members: $150
  • Pre-reqs: None
  • When: November 16th and 17th, 11:00AM – 12:30PM (EDT)
  • Duration: 2 days, 1.5 hours each day
  • Instructor: Greg Caswell

Abstract: Electrostatic Discharge (ESD) has been an issue in the electronics industry for years.  As gate geometries continue to get smaller and smaller the potential for ESD failures increases.  Similarly, the newest packaging technologies also make it easier to mishandle the components.  In some cases the failures are latent and don’t manifest themselves for a period of time making failure analysis and root cause assessments more difficult.

This course will address ESD Physics, a Classification System for Electronic Devices, ESD Protection Methods and Testing approaches.

ESD can be defined as a single-event, rapid transfer of electrostatic charge between two objects, usually resulting when two objects at different potentials come into direct contact with each other.  ESD can also occur when a high electrostatic field develops between two objects in close proximity. Also defined as an over-voltage event with a duration of 1 nanosecond to 1 microsecond that is primarily an issue during non-operational manufacturing and handling.

Topics addressed for the student will include:

  • ESD Models (CDM, HBM, MM, CBM)
  • Triboelectric Properties and Materials
  • The Industry Challenge
  • ESD Prevention (IC Level, Package Level, and System Level) and Specifications
  • Design Practices for ESD Management
  • ESD Scanning and Susceptibility Analysis Techniques
  • The Role of Capacitance
  • Diode and TVS Protection Schemes
  • PESD Devices
  • ESD Prevention in Manufacturing
    1. Sources of ESD
    2. Prevention Tools and Equipment
    3. Packaging and Humidity Effects
  • Failure Analysis Techniques
  • Distinguishing Between ESD and EOS

Target audience:  Engineers involved in the design, manufacturing, assembly, testing and/or reliability of electronic packages, circuit board assemblies

Benefits of attending

  • ESD Models (CDM, HBM, MM, CBM)
  • ESD Prevention (IC Level, Package Level, and System Level) and Specifications
  • Design Practices for ESD Management
  • Failure Analysis Techniques
  • Distinguishing Between ESD and EOS

Bio: Greg Caswell, a Lead Consulting Engineer for Ansys Corporation, is an industry recognized expert in the fields of SMT, advanced packaging, printed board fabrication, circuit card assembly, and bonding solutions using nanotechnology. He has been well-regarded as a leader in the electronics contract manufacturing and component packaging industries for the past 50 years. He has presented over 270 papers at conferences all over the world and has taught courses at IMAPS, SMTA and IPC events.  He helped design the 1st pick and place system used exclusively for SMT in 1978, edited and co-authored the 1st book on SMT in 1984 for ISHM and built the 1st SMT electronics launched into space.  Be on the lookout for his new book entitled Design for Excellence in Electronics Manufacturing due out in September 2020. Greg has won several awards including the IMAPS Lifetime Achievement Award in 2018, the ISHM Daniel C. Hughes Award (highest award given to an individual), ISHM Fellow of the Society Award and the Tracor Technical Innovation Award.

  • Price: IEEE Members: $80; Non-members: $100
  • Prereqs: None
  • Continuing Ed Credits: $5 extra/course
  • When: November 18th, 11:00AM – 1:00PM (EDT)
  • Duration: 1 day, 2 hours

Abstract:  Contamination issues in printed circuit board assemblies are a key driver in field failures resulting in corrosion and electrochemical migration failures.  Decreasing pitch sizes, increasing use of leadless packages, and electronic assembly in polluted or tropical environments are some trends which make contamination related failures more likely. To understand the challenge of contamination and cleanliness, one only needs to look at the many problems associated with high reliability environments, such as those encountered in automotive, and military applications. Particularly, high humidity exposure (85 % RH 85 C) can result in shorting occurring in less than 168 hours, due to dendritic growth and corrosion. Several of these failures are intermittent in nature, and result in no-fault-found (NFF) failures. This issue, in turn, can result from poor cleanliness both before solder mask and after soldering.  This course will present:

  • Overview of Contamination and Cleanliness
  • Drivers: Temperature Effects Humidity/Moisture Effects, Voltage and Electric Field
  • Sources of Contamination; PCB fab; Fluxes; Assembly; Handling; Use Environment
  • Mitigation Approaches and Conformal Coating

Target audience:  Engineers involved in the design, manufacturing, assembly, testing and/or reliability of electronic packages, circuit board assemblies

Benefits of attending

  • Drivers for cleanliness in printed circuit board corrosion failures
  • Methods for ensuring board cleanliness, test philosophy, mitigation
  • Conformal coating mitigation approaches

Bio:  Dock Brown, CRE

Dock Brown brings his more than 30 years of electronics reliability experience to clients of Ansys. Prior to joining Ansys, he spent 20 years at Medtronic where he most recently concentrated on cross business unit implementation of reliability initiatives for Class III medical devices. He was also responsible for supplier assessment and approval, on-going supplier audits, failure analysis, corrective actions, MRB, sampling, and ultimately full accountability for quality and reliability of COTS and custom parts and assemblies from a worldwide supplier base. Earlier in his career, Mr. Brown also spent time at Sundstrand Data Control where he led the implementation of the Boeing AQS program and with Olin Aerospace.

As a volunteer, he has been involved with ASQ, IEEE, IPC, and SMTA. He was the keynote speaker at the SMTA Cleaning Conference. He has taught design for reliability, tin whiskers, statistics, design of experiments, and contributed to standards development. He has won the SMTA Distinguished Speaker award and the SMTA Microelectronics Conference Best Paper award.

 

Upon entering the registration page, you will have the option of registering for one or more tutorials. We offer a 15% discount for 2-3 tutorials and 25% discount for 4-5 tutorials.  You will be able to choose your tutorials from the registration page. 

Instructor's Biographies

Greg Caswell, a Lead Consulting Engineer for Ansys Corporation, is an industry recognized expert in the fields of SMT, advanced packaging, printed board fabrication, circuit card assembly, and bonding solutions using nanotechnology. He has been well-regarded as a leader in the electronics contract manufacturing and component packaging industries for the past 50 years. He has presented over 270 papers at conferences all over the world and has taught courses at IMAPS, SMTA and IPC events. He helped design the 1st pick and place system used exclusively for SMT in 1978, edited and co-authored the 1st book on SMT in 1984 for ISHM and built the 1st SMT electronics launched into space. Be on the lookout for his new book entitled Design for Excellence in Electronics Manufacturing due out in September 2020. Greg has won several awards including the IMAPS Lifetime Achievement Award in 2018, the ISHM Daniel C. Hughes Award (highest award given to an individual), ISHM Fellow of the Society Award and the Tracor Technical Innovation Award.

Dock Brown, CRE

Dock Brown brings his more than 30 years of electronics reliability experience to clients of Ansys. Prior to joining Ansys, he spent 20 years at Medtronic where he most recently concentrated on cross business unit implementation of reliability initiatives for Class III medical devices. He was also responsible for supplier assessment and approval, on-going supplier audits, failure analysis, corrective actions, MRB, sampling, and ultimately full accountability for quality and reliability of COTS and custom parts and assemblies from a worldwide supplier base. Earlier in his career, Mr. Brown also spent time at Sundstrand Data Control where he led the implementation of the Boeing AQS program and with Olin Aerospace.

As a volunteer, he has been involved with ASQ, IEEE, IPC, and SMTA. He was the keynote speaker at the SMTA Cleaning Conference. He has taught design for reliability, tin whiskers, statistics, design of experiments, and contributed to standards development. He has won the SMTA Distinguished Speaker award and the SMTA Microelectronics Conference Best Paper award.