Discounts are offered to those who register for multiple verilog courses, (Verilog Foundations, System Verilog 101 and System Verilog 102). Call the IEEE office for details 781-245-5405.

CLASS DESCRIPTION:

SytemVerilog is an extensive set of language constructs to the IEEE 1364-2001 standard. It’s meant to aid in the creation and verification of models. There are two parts to the language extension. The first part covered by SV101, is new design constructs. SV102, this class, covers verification constructs. SystemVerilog102, like all CBE classes, is lab based.

There are over 30 verification labs/examples giving comprehensive “how to” examples of most SystemVerilog verification language constructs. There are working solutions for each lab and the students can use the lab database for developing their own assertions later. The class is also self paced. All the work can be done independently by the engineers, at their own computer, and at their own pace.

There are self-grading quizzes for each chapter that allow the student to see if he/she is learning the material.

The goals of this course are to make you familiar with the new part of the language.

Students taking SystremVerilog102 will have a 90-day access to it. The lab database you will be able to download and is yours to keep.

TARGET AUDIENCE:

Hardware engineers. SystemVerilog is the next stage in the evolution of Verilog. Every Verilog engineer will need to know this information.

PREREQUISITE:

Students must have a computer with Internet access. The class is written in HTML so any browser with a Flash (version 6 or higher) player will work.

To do the lab students must have access to an SystemVerilog simulator.

COURSE OUTLINE:

 SV102 Contains

Class Contents

SV102 - An Introduction

SystemVerilog - Verification Flow Overview

Immediate Assertions

lab1-- Immediate Assertions

Concurrent Assertions

lab2-- Concurrent Assertions

SystemVerilog Scheduling

lab3-- Scheduling

Quiz1

Sequences

Referencing a Sequence

lab4-- A Sequence Referencing A Sequence

Using Formal Arguments in a Sequence

lab5-- Using Formal Argument With A Sequence

Concatenation of Sequences

lab6-- Concatenation

Specifying a Range of Clock Ticks

lab7-- Clock Range

Unconditionally Extending a Sequence

lab8-- Unconditionally Extending A Sequence

Sequence Operators

Repetition

Consecutive Repetition

lab9-- Consecutive Repeats

Infinite Repeats

lab10-- Infinite Repeats

go to

lab11-- Goto Repeat Operator

Nonconsecutive Repetition

Anding

lab12-- Anding

Intersecting

lab13-- Intersecting

Oring

lab14-- Oring

Throughout

lab15-- Throughout

Within

lab16-- Within

Quiz2

Value Change Functions

$rose

lab17-- $rose

$fell

lab18-- $fell

$stable

lab19-- $stable

First match in a sequence

Ended

lab20-- Ended

Triggered

lab21-- Triggered

Properties

Using Formal Arguments

lab22-- Using Formal Arguments With A Property

Implications

Overlapping

lab23-- Overlapping Implications

Non-overlapping

lab24-- Non-Overlapping Implications

Quiz3

Inverting a property

lab25-- Inverting A Property

$past

lab26-- $past

disable iff

lab27-- disable iff

Assert Statements

Misc.

Action blocks

lab28-- Action Blocks

Severity

$fatal

lab29-- Severity-Fatal

$error

lab30-- Severity-Error

$warning

lab31-- Severity-Warning

$info

lab32-- Severity-Info

Cover Statement

lab33-- Cover

Binding an SVA module Parameter passing in a bind directive

Quiz4

DEVELOPERS BIOGRAPHY:

Jay Tyer, a graduate of WPI, has been teaching Verilog, Timing Analysis and various EDA tools for 17 years. He has been working in the development of online classes for several years.

REGISTRATION :

Ongoing - no "before" or "after" dates

Course Fee Schedule:

On-line Registration and Payment

Register and pay online.

Copyright © 2008 IEEE Boston Section. All rights reserved.
Maintained by R M Stelting

Updated Monday March 03, 2008