Discounts are offered to those who register for multiple verilog courses, (Verilog Foundations, System Verilog 101 and System Verilog 102). Call the IEEE office for details 781-245-5405.

CLASS DESCRIPTION:

Verilog is IEEE standard 1364. It is a Hardware Description Language that is the corner stone of much of the simulation world. Verilog Foundations is a comprehensive introduction to the IEEE 1364 (Verilog). The Verilog Foundations class has a slightly different approach to learning Verilog than other methods. There is a lecture section for each main topic. This presents a basic foundation for the language. What makes Verilog Foundations exciting is the emphasis on labs/examples. There are nearly 100 labs/examples giving comprehensive “how to” examples of most Verilog language constructs. There are working solutions for each lab and the students can use the lab database for developing their own models later. The class is also self paced. All the work can be done independently by the engineers, at their own computer, and at their own pace.

There are self-grading quizzes for each chapter that allow the student to see if he/she is learning the material.

The goals of this course are to make you familiar with developing a Verilog model, both behavioral and structural, using as much of the language as possible, and writing a verification test for that model.

Students taking Verilog Foundations will have a 90 day access to it. The lab database you will be able to download and is yours to keep.

TARGET AUDIENCE:

Hardware engineers. Verilog Foundations is good for the Verilog newbie or can be used as a good reference for the seasoned Verilog engineer.

PREREQUISITE:

Students must have a computer with internet access. The class is written in HTML so any browser with a Flash (version 6 or higher) player will work. If the free simulator is to be used then the computer must be a PC.

COURSE OUTLINE:

There are 12 lecture chapters in Verilog Foundations. They are:

1. Introduction

2. Foundations

3. Getting Started

4. Verilog Lexical Conventions

5. Data Types

6. Structural Modeling

7. User Defined Primitives

8. Behavioral Modeling

9. Memories

10. Operators

11. Modeling Timing Delays and Timing Checks

12. Synthesis Modeling

DEVELOPERS BIOGRAPHY:

Jay Tyer has been teaching Verilog, Timing Analysis and various EDA tools for 15 years. He has been working in the development of online classes for several years.

REGISTRATION :

Ongoing - no "before" or "after" dates

Course Fee Schedule:

On-line Registration and Payment

Register and pay online here.

[ Home ] [ Verilog 101 ] [ boston_section_and_cnec_chapter_chairs.htm ] [ cnec_officers.htm ] [ maine.htm ] [ new_hampshire_org.htm ] [ worcester_org.htm ]

Copyright © 2008 IEEE Boston Section. All rights reserved.
Maintained by R M Stelting

Updated Monday March 03, 2008