Free with Registration ($250 value):  Xilinx Spartan3-based FPGA development board, Simulink, ModelSim and Xilinx software/hardware demonstration development tools. Course notes will be available on the web.

Please Note: Please register by March 1, 2008 to guarantee your Xlinx board will be delivered by the first session.  Attendees registering after that date will have delay in receiving their boards.

Summary: FPGAs are becoming the implementation technology of choice for major United States employers involved in: Defense, Homeland Security, Energy, Communications, Aviation, Robotics, Factory Automation, Automotive, Public Transportation, Financial and Healthcare and other systems where dependable performance is a requirement.

“… the IEEE is exploring new areas where we can further assist technical professionals to distinguish themselves in the globally competitive environment.  One possibility is to develop TECHNICAL CURRENCY PROGRAMS   ”  Michael R. Lightner, IEEE President, “Enabling Members to Compete Globally”, IEEE Spectrum, March 2006.

To meet this need — the IEEE Boston Section with the support of the UNH Critical Infrastructure Dependability Laboratory {CIDLab} and the IEEE Global Education in Microelectronic Systems Initiative {I-GEMS} has established the on-going Technical Currency Series in Embedded Systems to complement its International Workshops in Mission-Critical Embedded Systems Engineering.  The Series seek to transfer a blend of the “state of the practice” in model-based design of embedded processing systems, with the “state of the art” in reconfigurable, programmable Systems-on-a-Chip.

Goal of the spring 18 hour course is to prepare attendees to have the required background to design and implement Field Programmable Gate Arrays {FPGA}-based Embedded Systems for software-defined radio, radar, sonar and flight controls, speech and image processing, medical equipment, robotics, public transportation and security systems and other Mission/Performance-Critical applications.

Approach: Link “state of the art” with the “state of the practice” through hands-on classroom lectures and demonstrations and interactive home-based labs in model-based design of embedded processing systems.

Intended Audience:  Faculty, engineers, and engineering managers interested in Embedded System Applications of FPGAs, SoC, PSoCs and networks of SoCs.

Enrollment:  Limited to 20

Benefits to attendees:

• Practical and hands-on exposure to US industry ‘best practices” in Development Tools, Design Techniques and Target Development Platforms.

• Introduction to novel applications of FPGAs for reconfigurable processing in sensor networks and heterogeneous processor systems.

• Become familiar with state-of-the-art in components and concepts in mission/ performance-critical FPGA-based embedded processing systems. 

Recommended Background: some experience with a high-level language, digital logic design, systems engineering or DSP applications. 

Course Outline:

Overview of Architectural Design Elements

• Lecture 1:  Hardware/Software Components, Spaanenburg

• Lecture 2:  Chip MultiProcessors, Spaanenburg

• Lecture 3:  Reconfigurable Computing, Spaanenburg

Introduction to FPGA-based Rapid Prototyping

• Lecture 4:  Levels of Abstraction, Rucinski

• Lecture 5:  Design Flow, Rucinski and Mosterman (The MathWorks)

• Lecture 6:  Tools for Design, Mosterman (The MathWorks)

IP Models, Test-benches and Core Repository with Demonstration

• Lecture 7:  IP Global Infrastructure, Kochanski

• Lecture 8:  Repository Demonstration, CMP-Techonline

System-on-Chip Infrastructure

• Lecture 9:  Trusted Intellectual Property (IP), Rucinski

• Lecture 10:  I-GEMS Design Environment, Kochanski

• Lecture 11:  Component/System Testing, Clark (Intellitech)

Hands-on Design

• Lecture 12:  Introduction to Spartan3 Board (NuHorizons)

• Lecture 13:  Design practice, Jack Gallagher (NuHorizons)

Mission-Critical Applications

• Lecture 14:  Heterogeneous Systems, Spaanenburg

• Lecture 15:  Mission-Critical Applications, Kochanski

• Lecture 16:  Perspectives and Wrap-Up, Kochanski

Decision/Cancel Date for this course is Tuesday, March 11, 2008

Course Fee Schedule:

On-line Registration and Payment

On-line registration for this course is closed, but you may register at the Holiday Inn Select, 15 Middlesex Canal Park Road, Woburn MA between 6:00PM – 6:30 on Wednesday, March 19th or by call the IEEE Office at 781-245-5405.

Copyright © 2008 IEEE Boston Section. All rights reserved.
Maintained by R M Stelting

Updated Monday March 17, 2008