Course:	FPGA-based Systems Engineering: Chip-scale to the Global-scale
Organized by:	Dr. Andrzej Rucinski, University of New Hampshire
instructors:	Dr. Kent Chamberlin, University of New Hampshire Dr. Ted Kochanski, University of New Hampshire Dr. Henk Spaanenburg, University of New Hampshire Dr. Pieter Mosterman, Senior Research Scientist, The MathWorks, Inc. CJ Clark CEO, Intellitech Corporation Steve Arms, CEO Microstrain
Date:	Wednesdays, 6 - 9:30PM, April 11, 18, 25, May 2, 9, 16
Location:	Holiday Inn Select, 15 Middlesex Canal Park Rd., Woburn, MA
texts:	Free with Registration.  Additional materials will be provided ($495 value): XUP Board, Simulink and (complete software/hardware development tools)
FPGA-based Systems Engineering: Chip-scale to the Global-scale
	C. “Max” Maxfield, The Design Warrior’s Guide to FPGAs, Newnes, Burlington, MA, 2004
	Clayton M. Christensen, The Innovator’s Dilemma: When New Technologies Cause Great Firms to Fail, Harvard Business School Press {1997}

“… the IEEE is exploring new areas where we can further assist technical professionals to distinguish themselves in the globally competitive environment. One possibility is to develop TECHNICAL CURRENCY PROGRAMS…”        Michael R. Lightner, IEEE President, “Enabling Members to Compete Globally”, IEEE Spectrum, March 2006

The IEEE, with educational coordination provided by the UNH and the University of Tennessee, in strategic partnership with The MathWorks, and with additional support of industry is offering this course in Field Programmable Gate Arrays, reconfigurable, Programmable-Systems-on-a-Chip and networks.  The goal of this course is to introduce “best practices” of the US high-tech industry for the design and implementation of FPGA-based microelectronic systems today and to be prepared for systems engineering based on reconfigurable processors and sensor networks with embedded processing.

This innovative hands-on and lecture-based course is designed for the practicing engineer and motivated by the challenges of the “flat world”, globalization and outsourcing facing today’s engineering profession and the New England technology-based economy.

Intended Audience: 

Faculty, engineers, and engineering managers interested in tools, techniques, and applications of FPGAs and PSoCs and networks of SoCs

Benefits:

Increasingly powerful and economical -- FPGAs have moved beyond prototyping tools for ASICs and “glue logic” into platforms for Signal Processing-intensive applications such as communications, radar, sonar and controls, speech and image processing. Participants will be introduced to many novel FPGA applications including reconfigurable processors for sensor networks.

Background:

Some experience with a High-level language {such as C, C++ or Fortran}, Digital Logic design, systems engineering or DSP applications.

Summary:

The goal is to prepare students to design and implement microelectronic systems using “best practices” of the US high tech industry today and be prepared for the revolutionary world of reconfigurable, programmable Systems-on-a-Chip and sensor-processor-networks.

Topics will include:

• Overview of Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), System-on-a-Chip (SoC), and Programmable SoC (PSoC) networks and constellations

• “rent-a-core” Intellectual Property (IP) IP testing, trust and design efficiency

• module design in VHDL and synthesis oriented implementation

• Co-design of SoC and Software within the appropriate software/firmware components development environment

• Top-level GUI-based systems design and simulations

• Integration of IP modules and sensor devices with an existing SoC

• Collaborative and distant learning techniques for distributed team management and design.

• In-situ and remote development and testing and optimization

• Reconfigurable processors and Programmable Systems on a Chip

Lectures: 

2 per evening based on the books, and unique lecture materials including XUP FPGA development board and Matlab/Simulink tools

April 11

1. Introduction: TPK, Rucinski;

2. Dr. Christine Shea, UNH; Outsourcing Economy

3. Sensor Technology and Enterpreneurism. S Arms Microstrain

April 18

4. Reconfigurable Computing:  H. Spaanenburg, UNH; XILINX

April 25

5. Levels of Abstraction:  A. Rucinski, UNH

6. Design Flow:  A. Rucinski, UNH

7. Tools for Design {Simulink}:  P. Mosterman The MathWorks

May 2

8. Intellectual Property (IP):  A. Rucinski, UNH

9. Open Standards:VIA, OCP:  D. Bouldin, University of Tennessee

10. Component System Testing:  CJClark. Intellitech

May 9

11. Component Tradeoffs and Trusted Circuits:  A. Rucinski, UNH

12. Design Excursions (SPADE):  H. Spaanenburg, UNH

13. Optimization (SPIRAL)

14. System Optimization

May 16

15. Heterogeneous Systems:  H. Spaanenburg, UNH; IEEE DHS Conference and
                                       Speakers; Intel, Middleware, multiple cores (?)

16. Upgrade/Updates Technology Transparency

17. Virtualization, Global development and education

18. Future perspectives and Wrap-up

Organizer and Lecturer’s Bios:

Andrzej Rucinski, Ph.D., Professor Department of Electrical and Computer Engineering and Institute for the Study of Earth, Oceans, and Space, Space Science Center, and Director Critical Infrastructure Dependability Laboratory, University of New Hampshire, Durham, NH and Chief Scientist National Infrastructure Institutes Center for Infrastructure Expertise Portsmouth, NH. Professor Rucinski received his M.Sc. from the Technical University of Odessa, USSR, and his Ph.D. in Technical Sciences from the Technical University of Gdansk, Poland. He has more than thirty years of teaching and research experience at Polish, Hungarian, French, Russian, Ukrainian, and American Universities. He spent a semester in 1993 with the Texas Instruments' FPGA Department in Dallas, Texas.  Since 1983 he has been a Professor at the University of New Hampshire where his research interests include: Critical Infrastructure, Collaborative Engineering, CAD, Computer Architecture, Design Methodologies, Distributed Computers, Engineering Curricula Development, Fault-Tolerant Computing and Networking, Knowledge Technology Transfer, Microelectronic Systems Design, Microelectronic Systems Testing, Technologies for Homeland Security and VLSI. He has more than 100 publications, including two edited and two written books. He organized numerous workshops and symposia in the US and abroad, e.g. he serves as the Program Chair of the IEEE International Conference on Microelectronics Systems Education. He organized and supervises a successful academic exchange program with the Budapest University of Technology and Economics, Hungary. He has been a Senior IEEE member and the Event Chair of the IEEE Technical Committee on Design Automation.

Thaddeus P. Kochanski) SB, Ph.D., (Ted), Affiliate Professor Electrical and Computer Engineering University of New Hampshire is an experimental physicist, systems engineering consultant and entrepreneur, with a passion for informal education, walking, and history.  He has contributed to wired and wireless sensor networks, soft x-ray, VUV, IR and cosmic-ray muon imaging, Giga-scale IC's, radar propagation, Ground Penetration Radar, data acquisition, signal processing and interactive multimedia.  His career spans: Tokamaks, University of Texas at Austin; Defense System Analysis, MIT Lincoln Laboratory; founder of Sensors Signals Systems and co-founder of several companies.  He received the IEEE Third Millennium Medal and the Gold award with Sapphire Gem of the Service League of the Boston Museum of Science.  Dr. Kochanski has been Program Chair 2002 - 2007 IEEE Conference on Technologies for Homeland Security.  In May, 2006, he was invited presenter “Sensor Networking and Synthetic Reality: from Air Defense Radars to Virtual Experimental Mine“ at 4th Conference on Information Technology Gdansk, Poland.  He recently launched the Critical Infrastructure Dependability Initiative under the auspices of the IEEE Boston Section.  He is senior past-Chair of the IEEE Boston Section, and permanent Chair of the Local Conferences Committee, Chair of the New Initiatives Committee and Chair of the Web subcommittee and member of the Publications Committee.

Dr. Henk Spaanenburg is an Affiliate Associate Professor at the University of New Hampshire, as well as the President and Chief Scientist of Heterogeneous Computing, LLC located in Durham, NH.  He has more than 25 years of experience in the development of high-performance computing architectures at Mercury Computer Systems, at Sanders, a Lockheed Martin Company, at Honeywell Technology Center (HTC), and at GE Aerospace Electronics Systems.  His current interest/mission is to realize the proper implementation/tooling of heterogeneous computing systems that include general-purpose computers, digital signal processors, reconfigurable computing (FPGAs) and fixed resources (ASICs).  Most recently, as a Chief Technology Strategist at Advanced Principles Group of Manchester, NH, he has been responsible for tracking relevant technology developments and for developing new research funding opportunities, many of them related to Homeland Security (border surveillance, stowaway detection, responder 3-D locator, and container security). 

Additional Outline Details

Lecture 1.  Introduction

Overview of Field Programmable Gate Arrays (FPGAs) design development In the global design world, Intellectual Property (IP), tools, globally distributed collaborative engineering development, reconfigurable sensors networks and applications

Lecture 2.  Outsourcing, Global Economy and entrepreneurship

Lecture 3  Microstrain, a successful small New England company built on integration and product innovation

Lecture 4.  Reconfigurable Computing

Positioned in computing densities between Application-Specific Integrated Circuits (ASICs) and Digital Signal Processors (DSPs), FPGAs provide increased flexibility in computational details such as degrees of parallelism and pipelining, as well as real-estate and power consumption over DSPs and General-Purpose (GP) microprocessors. 

Lecture 5.  Levels of Abstraction

It is a misconception to expect to be able to use FPGA personalization bit-level code, in order to update/upgrade.  Too many technology-specific design decisions have been made to get to that particular synthesized code pattern.  Only optimization at higher levels of abstraction will payoff in the long run. 

Lecture 6.  Design Flow

Design elements from UML down to VHDL, including SystemC, MathWorks’ Simulink and Xilinx’ SystemBuilder will be reviewed, as well as general design/test flows. 

Lecture 7.  Tools for Design

The state-of-the-art of design elements needed for collaborative design development, including verification, trade-off and optimization tools will be described and evaluated.

Lecture 8.  Intellectual Property (IP)

The IP business model and some of its limitations will be reviewed, several other business propositions such open model and fabless design companies will be analyzed. 

Lecture 9.  Open Standards: VIA, OCP, VSIA

Interface standards defined and developed for, in particular, System-on-Chip design will be reviewed and analyzed for compatibility to IP component development.

Lecture 10.  Component/System Testing

Intellitech a small New England company with a global customer base founded on delivering tools and Intellectual Property for testing.  Testability aspects of firmware components, including generation of test-vectors, assessment of coverage, JTAG testing and test monitor concept will be illustrated. 

Lecture 11.  Component Tradeoffs and Trusted Circuits

In heterogeneous computing environments, the constituting functions and subsystems can be implemented at various points along their respective design space tradeoff curves.  The use of more globally developed IC’s has increased the need for tools to support the “trustable” development of complex and performance sensitive applications. 

Lecture 12.  Design Excursions (SPADE)

In the University of Leiden [STEF02] approach particular computational instances have been “transformed” by small perturbations in the design space.  These techniques support a system designer in exploring alternative instances of an application mapped onto an architecture template. 

Lecture 13.  Optimization (SPIRAL)

A Carnegie Mellon University developed SPIRAL [PUCH05] program technique automatically generates high performance code that is tuned to the given platform.  SPIRAL generates code for a broad set of DSP transforms including the discrete Fourier transform, other trigonometric transforms, filter transforms, and discrete wavelet transforms. 

Lecture 14.  System Optimization

The total system solution can be evaluated for the right combination of design space points for their constituting elements.  This procedure within the total system constraint allows for an efficient process for increasing “benefits” for the least incremental “cost.”  These procedures especially facilitate the introduction of technology updates, since it allows for the reestablishment of the proper computational operating point for the combination of the old and new technology. 

Lecture 15.  Heterogeneous Systems

Heterogeneous processing systems currently contain a continuum of processing alternatives from general-purpose processors (GPP), to digital signal processors (DSP), to Field-Programmable Gate Arrays (FPGA) and Application-Specific Integrated Circuits (ASIC).  Especially the FPGA domain has recently produced its own range of architectural alternatives along that processing continuum spectrum. 

Lecture 16.  Upgrade/Updates, Technology Transparency

System developers must continue to reevaluate which combination of implementation alternatives will best meet their overall system requirements.  This question is not only important for the initial design, but also for subsequent technology updates and upgrades, especially when they have to be implemented in the same constrained real estate. 

Lecture 17.  Virtualization

A “virtual middleware” architecture can be carefully mapped onto an FPGA architecture.  This approach results in effective performance of the “virtual” architecture, with maximum parallelism and throughput.  To the system programmer the “virtual” (middleware) machine will become its programming environment.  Programming and code generation of the actual “virtual” machine will make use of conventional software tools, such as compilers and assemblers. 

Lecture 18  Summary and Wrap-up

Rapidly evolving FPGA and other PSOC technology is revolutionizing prototyping of micro circuits.  Today integrated nodes with processors, storage, sensors and/ or actuators are now being incorporated into large-scale networks.   When this hardware is combined with powerful, sophisticated and easy-to-use modeling and simulation tools the revolution will spread to the systems engineering environment.  The reconfigurability of processors further enables modern FPGAs to function as the foundation of high performance processors for many applications.

Support from:

UNH Department of ECE

IEEE Computer Society (Jim Aylor)

IEEE Critical Infrastructure Dependability Initiative and the IEEE Central New England Technology Council

The MathWorks, Inc. Natick, MA

Intellitech, Corporation Durham NH

Decision (Run/Cancel) Date for  this Courses is Tuesday, April 3, 2007

Course Fee Schedule:

On-line Registration and Payment

On-line registration is closed for this course, but registration is still available on-site between 5:30PM-6:00PM April 11, 2007 at the Holiday Inn Select, 15 Middlesex Canal Park, Woburn or by contacting the office at 781-245-5405.

Copyright © 2008 IEEE Boston Section. All rights reserved.
Maintained by R M Stelting

Updated Thursday August 16, 2007